Apparatus for facilitating scan testing of asynchronous logic ci

Details Apparatus for facilitating scan testing of asynchronous logic ci Apparatus for facilitating scan testing of asynchronous logic ci

1992-09-21

1994-02-08

Nguyen, Vinh

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

With rotor

324 731, 371 221, 371 223, G01R 3128

Patent

active

052851532

ABSTRACT:
Scan testing of asynchronous logic circuitry is facilitated by gating off the asynchronous inputs to flip-flops during scan testing. If desired, the asynchronous inputs which are gated off in this manner may themselves be tested by connecting them to one or more output terminals or scan registers during testing. Alternatively, the asynchronous inputs which are gated could be tested by selectively enabling the signals at strategic points during scan testing. The number of input terminals required to control the test mode may be reduced by providing registers for storing test control signals applied to normal input terminals at the beginning of a test cycle. Once these test control signals are stored, the normal input terminals are free to return to their normal use.

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