Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-04-05
2002-04-16
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S714000, C438S720000, C438S732000, C438S742000
Reexamination Certificate
active
06372654
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method and an apparatus for fabricating a semiconductor device, and more particularly to such a method including a step of patterning multi-layered metal wirings composed of aluminum, through inducive coupling plasma, and also to such an apparatus for generating inducive coupling plasma to thereby pattern multi-layered metal wirings.
DESCRIPTION OF THE RELATED ART
A wiring layer is required to be patterned in a size smaller and smaller with enhancement in integration of LSI. In order to transfer a small-sized mask pattern to a layer such as an electrically conductive layer and an insulating layer, such a layer is usually etched by anisotropic dry etching which makes use of plasma, such as reactive ion etching (RIE) and electron cyclotron resonance (ECR) plasma etching.
On the other hand, as a semiconductor device has been fabricated in a size smaller and smaller, a gate insulating film in an insulating gate type field effect transistor (FET) is made thinner and thinner. For instance, a latest gate insulating film is designed to have a thickness of 10 nm or smaller. Such a thin gate insulating film is likely to be damaged by just small electric stress.
An electrically conductive layer is usually composed of aluminum or alloy thereof. There are known a couple of anisotropic dry etching methods in which plasma is generated, as methods for dry-etching such an electrically conductive layer.
For instance, in one of such dry etching methods, an electrically conductive layer composed of aluminum or alloy thereof, formed on a semiconductor substrate, is etched with a patterned resist film being used as a mask through plasma generated from a mixture gas of and Cl
2
gas. In plasma, the BCl
3
gas exists as BCl
2+
, and the Cl
2
gas produces Cl radicals. These Cl species make chemical reaction with aluminum or alloy thereof of which the electrically conductive layer is composed, to thereby generate volatile AlCl
3
having high vapor pressure. The thus generated volatile AlCl
3
is evaporated, and resultingly, the electrically conductive layer composed of aluminum or alloy thereof is etched.
In a plasma etching process, electrons as well as the above-mentioned Cl ion species are incident to a substrate. If there is a difference between incident positive and negative electric charges, electric charges are accumulated in an electrically conductive layer which is formed on a gate insulating film and is electrically insulated from the substrate. As a result, there is generated a difference in a voltage between the electrically conductive layer and the substrate. Such a difference in a voltage allows tunnel current to pass through the gate insulating film, resulting in that dielectric characteristics of the gate insulating film is varied, and hence, the gate insulating film might reach dielectric breakdown.
As mentioned above, a plasma etching process in which a gate electrode or an electrically conductive layer formed on a gate insulating film, and electrically conductive layers electrically connected to the gate electrode (hereinafter, a gate electrode and such electrically conductive layers are referred to as “gate wirings”) are charged up, that is, electric charges are accumulated in the gate wirings, might cause the gate insulating film to be damaged. A plasma etching process is carried out, for instance, when a gate wiring layer is patterned, when a contact hole is formed reaching a gate wiring layer, when a contact hole reaching a gate insulating layer is cleaned by sputter etching, and when plasma-enhance chemical vapor deposition is carried out to a surface of a substrate at which a gate wiring layer partially appears.
In addition, if plasma formed non-uniformly above a semiconductor substrate, there would be generated a difference between an ion current and an electron current both to be introduced into the semiconductor substrate. This difference might allow a tunnel current to pass through a gate insulating film.
As a semiconductor device is integrated highly and highly, an antenna ratio defined as a ratio of an area of a gate insulating film to an area of an electrically conductive layer composed of aluminum or alloy thereof is significantly increased. When an electrically conductive film having a high antenna ratio is to be etched by a plasma etching process, small non-uniformity in plasma might allow much tunnel current to pass through a gate insulating film.
It has been reported that even if there is generated plasma having a profile of electric charges which is uniform to a flat surface, there would occur charging damage called electron shading damage inherent to high-density plasma etching, in a plasma etching step in which a resist mask including an aperture having a high aspect ratio, that is, a narrow space.
The above-mentioned electron shading damage is caused by both charge imbalance between ion flux and electron flux at a bottom of a space formed between wirings, and micro-loading which is one of characteristics of dry etching.
Hereinbelow is explained the electron shading damage with reference to FIG.
1
.
With reference to
FIG. 1
, in ion sheath formed in an electrode to which RF voltage is applied when plasma is discharged, ion flux
101
is anisotropically incident to spaces formed between adjacent metal wirings
105
, whereas electron flux
102
is isotropically incident to the spaces in the same manner as electron flux being incident in plasma bulk.
Anisotropy of the electron flux
102
causes a majority of electrons
104
is incident onto sidewalls of an insulating mask such as resist masks
103
. As a result, the electrons
104
are much accumulated on the sidewalls of the resist masks
103
to thereby generate a negative voltage on the resist masks
103
. As a space between the resist masks
103
is small, that is, as an aspect ratio is high, negative voltages generated on the sidewalls of the resist masks
103
overlap each other, resulting in that the negative voltages generated around the resist masks
103
are further increased. Accordingly, an amount of the electron flux
102
reaching bottoms
106
of holes formed between the adjacent resist masks
103
is significantly reduced. Thus, there is generated imbalance between the electron flux
102
and the ion flux
101
at the bottoms
106
of the holes having a high aspect ratio.
Dry etching has many characteristics, one of which is micro-loading effect. Herein, the micro-loading effect is a phenomenon in which an etching rate varies in dependence on an aspect ratio. In general, an etching rate lowers as an aspect ratio increases. Hence, though the metal wirings
105
have been already etched in portions having a relatively low aspect ratio, the bottoms
106
of the holes having a relatively high aspect ratio have not been etched yet. In a period of time after the portions having a relatively low aspect ratio have been etched for removal until the bottoms
106
have been completely etched (hereinafter, such a period of time is referred to as “injection time”), positive electric charges are accumulated on the bottoms
106
due to charge imbalance.
As a result, a gate electrode
108
has a positive voltage relative to a silicon substrate
109
. Then, electrons
111
are injected into the gate electrode
108
from the silicon substrate
109
through a gate oxide film
110
in order to dissolve the charge imbalance. A current caused by the injected electrons
111
is in proportion to both a gate voltage and the above-mentioned injection time.
If a current caused by the injected electrons
111
flow excessively through the gate oxide film
110
, the gate oxide film
110
would be degraded and/or damaged.
The explanation mentioned above is the reason why the electron shading damage occurs.
Many attempts have been made to uniformize plasma by generating plasma by virtue of pulse modulation. For instance, Japanese Unexamined Patent Publications Nos. 6-267900 and 8-181125 have suggested methods of etching a wiring layer. In the met
McGinn & Gibb PLLC
NEC Corporation
Tran Binh X
Utech Benjamin L.
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