Apparatus for extracting instruction specific bytes from an inst

Details Apparatus for extracting instruction specific bytes from an inst Apparatus for extracting instruction specific bytes from an inst

1997-12-12

1999-03-30

Pan, Daniel H.

395382, 395384, 395385, 395386, 395387, 395388, 39580005, 39580024, 39580025, 39580027, 395856, 395860, 395869, 395871, G06F 1300

Patent

active

058900063

ABSTRACT:
A superscalar microprocessor predecodes instruction data to identify the boundaries of instructions and the type of instruction. In one embodiment, to expedite the dispatch of instructions, the first microcode instruction of the cache line is identified during predecode and stored as a microcode pointer. When the cache line is scanned for dispatch, the microcode pointer is used to identify the first microcode instruction which is conveyed to the MROM unit. In another embodiment, the first scanned instruction is predicted to be a microcode instruction and is dispatched to the MROM unit. A microcode scan circuit uses the microcode pointer and the functional bits of the predecode data to multiplex instruction specific bytes of the first microcode instruction to the MROM unit. If the predicted first microcode instruction is not the actual first microcode instruction, then in a subsequent clock cycle, the actual microcode instruction is dispatched the MROM unit and the incorrectly predicted microcode instruction is canceled.

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patent: 5581718 (1996-12-01), Grochowski
patent: 5689672 (1997-11-01), Witt et al.
patent: 5740392 (1998-04-01), Brennan

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