Apparatus for expediting sub-unit and memory communications in a

Details Apparatus for expediting sub-unit and memory communications in a Apparatus for expediting sub-unit and memory communications in a

1983-06-02

1986-12-16

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 900

Patent

active

046301941

ABSTRACT:
Bus command generation apparatus is provided for a microprocessor implemented data processing system that uses a multibyte width system bus requiring a bus command byte since a complete bus command byte is ordinarily unavailable directly from a microprocessor. A bus command register is loaded with a preliminary bus command, certain bits of which are then modified in accordance with the operation to be performed. The limited command information available from the microprocessor that controls I/O operations is utilized to modify the preliminary bus command bytes without any need to access memory for bus command information. The bus command generation apparatus is adapted to pass a preliminary bus command byte unaltered, under predefined conditions, to the system bus.

REFERENCES:
patent: 4340933 (1982-07-01), Miu et al.

Affiliated with

Also associated with

Rating

Apparatus for expediting sub-unit and memory communications in a does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for expediting sub-unit and memory communications in a, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for expediting sub-unit and memory communications in a will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-249460