Apparatus for executing add/sub operations between IEEE standard

Details Apparatus for executing add/sub operations between IEEE standard Apparatus for executing add/sub operations between IEEE standard

1992-11-24

1994-08-09

Malzahn, David H.

Boots, shoes, and leggings

G06F 750

Patent

active

053372654

ABSTRACT:
A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0.
In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the "carry out" output. The "Force Carry" input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.

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patent: 5086405 (1992-02-01), Chung et al.
patent: 5197023 (1993-03-01), Nakayama
patent: 5247471 (1993-09-01), Hilker et al.

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