Apparatus for executing a RISC store and RI instruction pair in

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36423223, 3642624, 364263, 3642631, 364DIG1, G06F 928

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active

052934993

ABSTRACT:
A processor for a SPARC based RISC computer including a central processing unit including a register file having a pair of read ports and a write port, an instruction register for holding an instruction including addresses of registers to be read and written to, a multiplexor, and apparatus for controlling the multiplexor to transfer the address from a write position of the instruction register to the register file such that the information stored in the addressed register is transferred out of the register file through one of the read ports on the clock cycle following a store instruction.

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