Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate
1995-03-22
2001-07-03
Banankhah, Majid (Department: 2151)
Electrical computers and digital processing systems: multicomput
Computer-to-computer data routing
Least weight routing
C709S241000, C709S241000
Reexamination Certificate
active
06256658
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to computer systems, and more specifically to a computer system which allows code written in incompatible object codes to be mixed in a single program for execution.
BACKGROUND OF THE INVENTION
When a new computer processor is developed, existing applications or programs, herein “applications”, which executed properly on a prior computer processor may not execute properly on the new computer processor. These old, or in other words, non-native applications are typically “ported”, i.e. rewritten or translated, to run on the new processor. Usually, until an application is ported, it is unable to take advantage of any beneficial features in the new processor. Depending on the amount of effort required to port the application, there may be a substantial amount of time lost before an application can benefit from the new processor.
Typically a computer system having the new computer processor will have a separate environment for running “old” applications written for the old processor. This environment is called a “compatibility box”. In these systems there is substantially no interaction between the compatibility box and the new processor environment, otherwise known as the “native” environment. Thus, “old” applications can not take advantage of performance benefits and other advantageous features available in the native environment.
Some computer systems have emulators which permit the computer system to execute code which is written for a processor other than the processor which is native to the computer system. Typically, these emulators assume a single runtime environment, that is to say that they assume that the conventions for invoking program procedures and performing stack manipulations are common to both the native and non-native or emulated code. These emulators typically just alter the instructions set and are not structured to handle two different types of program object code which have different routine calling and stack manipulation conventions. For example, these emulators are ill-equipped to handle CISC (“Complex Instruction Set Computer”) such as Motorola 68000 (herein “68K”) and RISC (“Reduced Instruction Set Computer”) code (such as the IBM PowerPC or the IBM RISC System/6000) herein “RISC” simultaneously on the same machine. PowerPC, IBM and RISC System/6000 are registered trademarks of International Business Machines Corporation, Armonk, N.Y.
Background information on CISC machines can be found in “Inside Macintosh”, Vols. I-VI, published by Addison-Wesley Publishing Co., 1985-1991, the disclosure of which is hereby incorporated by reference. Background information on IBM's RISC System/6000 machine can be found in “Machine organization of the IBM RISC System/6000 processor” by Gregory F. Grohoski and “IBM RISC System/6000 processor architecture” by R. R. Oehler and R. D Groves, both articles published in IBM Journal of research and Development, Vol. 34, No. 1,January 1990, at pp. 37-58 and pp. 23-36, respectively, the disclosures of which are hereby incorporated by reference.
Background information on IBM's RISC subroutine linkage conventions may be found in “AIX XL FORTRAN Compiler/6000 User's Guide Version 2.3”, Chapter 10, September 1992, International Business Machines Corporation, Armonk, N.Y. and in “Managing programs and libraries in AIX Version 3 for RISC System/6000 processors”, by Marc A. Auslander, published in IBM Journal of Research of Development, Vol. 34, No. 1, January 1990, pp. 98-104, the disclosures of which are hereby incorporated by reference. AIX is a trademark of International Business Machines Corporation.
In a 68K environment, a procedure pointer addresses the 68K routine itself, but in some other environments such as RISC, a procedure pointer addresses a structure such as data structure or executable code which contains among other information an address of the routine. In the RISC System/6000 environment, the structure contains an address of an entry point to the routine,and address of a table of contents for a module in which that routine is bound and a pointer to an environment for languages that require such a pointer. If the RISC code were conformed to match the 68K runtime model, no advantages of the RISC instruction set could be used.
In some prior computer systems, to execute on a single processor two on more programming languages having different calling conventions the programming languages are altered to each use a common baseline calling convention. In other prior systems, a programming language is structured to explicitly handle the different calling conventions of the other languages.
Typically, computer system which emulate prior processors in addition to supporting a new native processor only support one environment at a time. In other words, applications running simultaneously are executed in the same processor environment of mode. For example, when multiple applications are being executed at the same time, even if only one of the applications is written for a non-native processing environment and all of the other applications are designed for the native environment, ALL of the applications will be executed in an emulated environment appropriate for that one non-native application. Thus none of those applications benefit from the advantages provided by the new, native processor.
SUMMARY OF THE INVENTION
It is a principal object of this invention to provide a transparent mechanism for switching between a plurality of processor modes such that application or program can access any processor mode.
Another object of this invention is to provide a mechanism for an application to explicitly access a particular processor mode.
Another object of this invention is to provide a mechanism for identifying the appropriate processor mode on which to execute a particular program segment.
Another object of this invention is to support multiple applications in multiple environments at substantially the same time.
Another object of this invention is to permit a computer system to execute system software which is based in part on plurality of processors.
Another object of this invention is to allow an executing program to change from a first processor mode to a second processor mode without changing the program's code.
This invention provides a method and apparatus for switching between execution of a plurality of object code types having different conventions for invoking program procedures and performing stack manipulations. The invention may also be used to switch between two or more different calling conventions within a single object code type. Briefly according to the invention, a computer system comprises a means for executing instructions for one or more code types, a routine descriptor, a stack switch frame, and a mode switching mechanism for switching between processor types or code types, herein referred to as “modes”. The invention may also include other mechanisms for creating, manipulating and setting information within a routine descriptor and for accessing information associated with a particular routine descriptor.
The means for executing instructions may be for example a central processing unit and an emulator, a plurality of central processing units, or a single central processing unit having a plurality of modes of operation. The means for executing instructions further includes any related software used to execute the instructions.
A routine descriptor describes the characteristics of a program segment or portion of code such as its processor or code type and calling convention. Optionally, a routine descriptor can describe a plurality of program segments performing substantially the same function, but implemented in a variety of processor or code types and calling conventions.
A routine descriptor contains, among other information, a “mixed mode” field which is set to a specific, predetermined value such as an illegal instruction or an illegal memory address. The value of the mixed mode field may vary depending upon the means for executing i
Eidt Erik L.
Jones Bruce K.
Lillich Alan W.
Mourey Jean-Charles D.
Parent Sean R.
Apple Computer Inc.
Banankhah Majid
Workman Helene Plotka
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