Apparatus for enabling PLL to lock on to a correct frequency...

Details Apparatus for enabling PLL to lock on to a correct frequency... Apparatus for enabling PLL to lock on to a correct frequency...

2006-10-17

2006-10-17

Patel, Gautam R. (Department: 2627)

Dynamic information storage or retrieval

Control of storage or retrieval operation by a control...

Control of information signal processing channel

C369S059210

Reexamination Certificate

active

07123560

ABSTRACT:
In a PLL circuit, a phase error of a reproduced signal is extracted in either a way based on a zero-cross timing or a way based on a self-running timing. A decision is made as to whether the reproduced signal is in a continuous-wave interval where an inversion period of the reproduced signal remains constant or in a random-wave interval where the inversion period of the reproduced signal varies at random. When the reproduced signal is in a continuous-wave interval, a phase error is extracted on the self-running-timing basis. When the reproduced signal is in a random-wave interval, a phase error is extracted on the zero-cross-timing basis. A continuous-wave interval may be replaced by a specified-pattern repetition interval where the inversion period of the reproduced signal changes in accordance with a repetition of a specified pattern.

REFERENCES:
patent: 6445662 (2002-09-01), Tonami
patent: 6833875 (2004-12-01), Yang et al.

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