Data processing: structural design – modeling – simulation – and em – Emulation – Of peripheral device
Reexamination Certificate
2005-01-11
2005-01-11
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Emulation
Of peripheral device
C702S115000, C714S725000, C716S030000
Reexamination Certificate
active
06842729
ABSTRACT:
A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.
REFERENCES:
patent: 3106698 (1963-10-01), Unger
patent: 3287702 (1966-11-01), Borck, Jr. et al.
patent: 3287703 (1966-11-01), Slotnick
patent: 3473160 (1969-10-01), Wahlstrom
patent: 3810577 (1974-05-01), Drescher et al.
patent: 3928730 (1975-12-01), Agaard et al.
patent: 3955180 (1976-05-01), Hirtle
patent: 4020469 (1977-04-01), Manning
patent: 4032899 (1977-06-01), Jenny et al.
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4315315 (1982-02-01), Kossiakoff
patent: 4357678 (1982-11-01), Davis
patent: 4386403 (1983-05-01), Hsieh et al.
patent: 4404635 (1983-09-01), Flaker
patent: 4459694 (1984-07-01), Ueno et al.
patent: 4488354 (1984-12-01), Chan et al.
patent: 4503386 (1985-03-01), DasGupta et al.
patent: 4510602 (1985-04-01), Engdahl et al.
patent: 4524240 (1985-06-01), Stock et al.
patent: 4525789 (1985-07-01), Kemper et al.
patent: 4527115 (1985-07-01), Mehrotra et al.
patent: 4527249 (1985-07-01), Van Brunt
patent: 4539564 (1985-09-01), Smithson
patent: 4541071 (1985-09-01), Ohmori
patent: 4577276 (1986-03-01), Dunlop et al.
patent: 4578761 (1986-03-01), Gray
patent: 4583169 (1986-04-01), Cooledge
patent: 4587625 (1986-05-01), Marino, Jr. et al.
patent: 4593363 (1986-06-01), Burstein et al.
patent: 4600846 (1986-07-01), Burrows
patent: 4612618 (1986-09-01), Pryor et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4621339 (1986-11-01), Wagner et al.
patent: 4642487 (1987-02-01), Carter
patent: 4656580 (1987-04-01), Hitchcock, Sr. et al.
patent: 4656592 (1987-04-01), Spaanenburg et al.
patent: 4674089 (1987-06-01), Poret et al.
patent: 4675832 (1987-06-01), Robinson et al.
patent: 4695740 (1987-09-01), Carter
patent: 4695950 (1987-09-01), Brandt et al.
patent: 4695968 (1987-09-01), Sullivan, II et al.
patent: 4695999 (1987-09-01), Lebizay
patent: 4697241 (1987-09-01), Lavi
patent: 4700187 (1987-10-01), Furtek
patent: 4706216 (1987-11-01), Carter
patent: 4713557 (1987-12-01), Carter
patent: 4722084 (1988-01-01), Morton
patent: 4725835 (1988-02-01), Schreiner et al.
patent: 4725971 (1988-02-01), Doshi et al.
patent: 4736338 (1988-04-01), Saxe et al.
patent: 4740919 (1988-04-01), Elmer
patent: 4744084 (1988-05-01), Beck et al.
patent: 4747102 (1988-05-01), Funatsu
patent: 4752887 (1988-06-01), Kuwahara
patent: 4758745 (1988-07-01), El Gamal et al.
patent: 4758985 (1988-07-01), Carter
patent: 4761768 (1988-08-01), Turner et al.
patent: 4766569 (1988-08-01), Turner et al.
patent: 4768196 (1988-08-01), Jou et al.
patent: 4769817 (1988-09-01), Krohn et al.
patent: 4777606 (1988-10-01), Fournier
patent: 4782440 (1988-11-01), Nomizu et al.
patent: 4782461 (1988-11-01), Mick et al.
patent: 4786904 (1988-11-01), Graham, III et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4787062 (1988-11-01), Nei et al.
patent: 4791602 (1988-12-01), Resnick
patent: 6377911 (2002-04-01), Sample et al.
patent: 0217291 (1986-09-01), None
patent: 1444084 (1976-07-01), None
patent: 218220 (1986-09-01), None
patent: 2180382 (1987-03-01), None
patent: 58-147236 (1983-09-01), None
patent: 58-147237 (1983-09-01), None
patent: 58-205870 (1983-11-01), None
patent: 59-161839 (1984-09-01), None
“The Homogenous Computational Medium; New Technology for Computation”, Concurrent Logic Inc., Jan. 26, 1987.
Spandorfer, “Synthesis of Logic Functions on an Array of Integrated Circuits”, Contract Report AFCRI-6-6-298, Oct. 31, 1965.
J.Babb, R.Tessier, A.Agarwal, Virtual Wires: Overcoming Pin Limitation.
M.McFarland, A.Parker, R.Camposano “The High-Level Synthesis of Digital Systems”.
T.Payne; Automated Partitioning of Hierarchically Specified Digital Systems; May 1981.
Tham, “Parallel Processing CAD Applications”, IEEE Design & Test of Computer, Oct. 1987, pp. 13-17.
Agrawal, et al. “MARS: A Multiprocessor-Based Programmable Accelerator”, IEEE Design & Test Computers, Oct. 1987, pp. 28-38.
Manning “An Approach to Highly Integrated, Computer-Maintained Cellular Arrays”, IEEE Transactions on Computers, vol. C-26, Jun. 1977, pp. 536-552.
Manning, “Automatic Test, Configuration, and Repair of Cellular Arrays”, Doctoral Thesis MAC TR-151 (MIT), Jun. 1975.
A. Agarwal; Virtual Wires: A Technology for Massive Multi-FPGA Systems; Virtual Machine Works.
Ravenscroft, Function Language Extractor and Boolean Generator IEEE 1986, pp. 120-123.
Shoup, “Programmable Cellular Logic Arrays,” Doctoral Thesis (Carnegie-Mellon University; DARPA contract No. F44620-67-C0058), Mar. 1970.
Shoup, “Programmable Cellular Logic,” undated, pp. 27-281.
Wynn, “In-Circuit Emulation for ASIC-Based Designs” VLSI Systems Design, Oct. 1986, pp. 38-45.
Minnick, “Survey of Microcellular Research,” Stanford Research Institute Project 5876 (Contract AF 19(628)-5828, Jul. 1966.
Siegel “The Design of a Logic Simulation Accelerator”, Oct. 1985 pp 76-86 VLSI Systems Design.
Minnick, “A Programmable Cellular Array,” undated, pp. 25-26.
Minnick, “Cutpoint Cellular Logic,” IEEE Transactions on Electronic Comuters, Dec. 1964, pp. 658-698.
Jump, et al. “Microprogrammed Arrays,” IEEE Transactions on Computers, vol. C-21, No. 9, Sep. 1972, pp. 974-984.
Gentile, et al. “Design of Switches for Self-Reconfiguring VLSO Array Structures,” Microprocessing and Microprogramming, North-Holland, 1984, pp. 99-108.
Preparata, “The Cube-Connected Cycles: A Versatile Network for Parallel Computation,” Communications of the ACM, May, 1981, pp. 300-309.
Clos, “A Study of Non-Blocking Switching Networks,” The Bell System Technical Journal, Mar. 1953, pp. 126-144.
Masson, “A Sampler of Circuit Switching Networks” Computer, Jun. 1979, pp. 32-48.
“Plus Logic FPGA2020 Field Programmable Gate Array” Brochure by Pius Logic, San Jose, CA, pp. 1-13.
Schmitz, “Emulation of VLSI Devices Using LCAs,” VLSI systems Design, May 20, 1987, pp. 54-62.
Abramovici, et al., “A Logic Simulation Machine,” 19thDesign Automation Conference, Paper 7.4, 1982, pp. 65-73.
Hennessy, “Partitioning Programmable Logic Arrays,” undated, pp. 180-181.
DeMicheli, et al., “Topological Partitioning of Programmable Logic Arrays,” undated, pp. 182-183.
Hou, et al., “A High Level Synthesis Tool For Systolic Designs,” IEEE, 1988, pp. 665-673.
“Gate Station Reference Manual,” Mentor Graphics Corp., 1987 (excerpts).
Dussault, et al., “A High Level Synthesis Tool for MOS Chip Design,” 21stDesign Automation conference, 1984, IEEE, pp. 308-314.
DeMicheli, et al., “Hercules—a System for High Level Synthesis,” 25thACM/IEEE Design Automation Conference, 1988, pp. 483-488.
Donnell, “Corsspoint Switch: A PLD Approach,” Digital Design, Jul. 1986 pp. 40-44.
Beresford, “Hard Facts, Soft ASICS,” VLSI Systems Design, Dec. 1986, p. 8.
Snyder, “Introduction to the Configurable, Highly Parallel Computer,” Report CSD-TR-351, Office of Naval Research Contracts N00014-80-K-0816 and N00014-8-1-K-0360, Nov. 1980.
Paleski, et al., “Logic Partitioning for Minimizing Gate Arrays,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. CAD-2, No. 2, Apr. 1983.
Chin, et al. A Dynamically Reconfigurable Interconnect Chip; IEEE International Solid State Circuits conference, 1987; pp 276-277 &
D'Amour Michael R.
Payne Thomas S.
Sample Stephen P.
Frejd Russell
Orrick Herrington & Sutcliffe LLP
Quickturn Design Systems Inc.
LandOfFree
Apparatus for emulation of electronic systems does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for emulation of electronic systems, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for emulation of electronic systems will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3430865