Apparatus for eliminating leakage current of a low Vt device...

Details Apparatus for eliminating leakage current of a low Vt device... Apparatus for eliminating leakage current of a low Vt device...

2006-10-06

2008-11-18

Pham, Ly D (Department: 2827)

Static information storage and retrieval

Floating gate

Particular connection

C365S154000, C365S189050

Reexamination Certificate

active

07453725

ABSTRACT:
An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.

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