Electricity: measuring and testing – Fault detecting in electric circuits and of electric components – Of individual circuit component or element
Reexamination Certificate
1998-10-13
2001-04-03
Karlsen, Ernest (Department: 2858)
Electricity: measuring and testing
Fault detecting in electric circuits and of electric components
Of individual circuit component or element
C324S762010
Reexamination Certificate
active
06211690
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates in general to an apparatus for testing microelectronic elements, and more particularly, to an interposer for testing microelectronic elements in the nature of bare printed circuits having a plurality of contacts arranged in matrices having normal and high contact pitch densities.
Electrical testing of microelectronic elements such as circuit elements and printed circuit boards, is typically conducted using drilled plates including dielectric materials. The drilled openings serve to guide spring loaded probes of the test fixture to test point locations which are of interest on the printed circuit. The probes may be either “hard” or permanently wired or they may be removable as is the case in systems where the text fixture is placed on a standard base grid of programmable test points.
FIG. 1
shows a printed circuit board
1
having a standard grid of test points
2
whereby all of the test probes
3
of the text fixture
4
are in alignment therewith. The system commonly uses “pogo pins” in a “bed-of-nails” configuration as shown. This system has reliably served the testing needs of the printed circuit industry for many years, however, at present there is a need to advance the state of the art to address two important issues: 1) the increasing density of test points associated with newer surface mount components, and 2) the need to translate grid points from a nominal 0.100″ to grid pitches which may be either metric based or English based, often on the same circuit. It is the express purpose of this invention to address these needs by providing a low cost system for electrically testing local high contact pitch density areas of a printed circuit board. The system should be able to simultaneously test both high contact pitch density areas and normal contact pitch density areas on a circuit board.
FIG. 2
shows one system presently being used to test the high density areas of a printed circuit board. As is evident from
FIG. 2
, these fixtures are considerably complex. In order to contact the test points located in high density areas, some of the test probes
5
are angled toward one another so that the tops of the probes are closer together. However, this test system has additional cost in terms of both electronic and mechanical elements, and most of the test points will be unused most of the time.
Accordingly, there is an unsolved need for a test fixture which can accommodate microelectronic elements such as printed circuits and the like having contacts disposed thereon, for example, in both high contact pitch density and normal contact pitch density.
SUMMARY OF THE INVENTION
The present invention seeks to mitigate the major difficulties and inefficiencies of the above-described systems by providing for the customization of the circuit test fixture using lithographic techniques to produce a planar yet compliant test fixture rather than to use discrete test pins. The test fixture is formed using a flexible substrate. The circuit points for the test fixture are fabricated by any of a number of different mechanical techniques but would typically be formed by either electroforming, etching or a combination of the two. The actual test points are made compliant by backing the points with a compliant material. A resilient layer could also be included, such as a metal spring foil having shape memory characteristics to provide a restorative spring force for resilience. Spring foils can be super elastic materials such as certain nickel titanium alloys known as Nitinol®. The test fixture according to preferred embodiments of the present invention may be used in combination with existing test fixtures so that the test probes do not have to be angled to engage test points located in high density areas.
The “bed of nails” test fixtures described above typically utilize DC signals since they are less affected by the impedance added by the “Spring Pins” normally used in test fixtures; however, DC signals are of limited value when evaluating high frequency applications. However, when an AC signal is used, the spring in the probe looks like an inductor to the AC signal. It is possible to reduce the inductance by reducing the travel of the probe. Some test systems may also utilize a spring probe at the connection of the fixture to the tester. This method could also be obviated by using the approach described herein.
In accordance with one embodiment of the present invention there is disclosed an interposer for testing a microelectronic element having a plurality of contacts. The interposer includes a substrate having a top surface and a bottom surface, at least one conductive lead extending on the top surface between a first and second position, a first opening extending through the substrate from the bottom surface to a location on the top surface in communication with the conductive lead at the first position, the conductive lead at the second position registrable with one of the contacts on the microelectronic element, the opening operative for receiving a test probe therein for engagement with the conductive lead at the first position.
In accordance with another embodiment of the present invention there is disclosed an interposer for testing a microelectronic element having a plurality of contacts. The interposer includes a substrate having a top surface and a bottom surface, at least one conductive lead extending along one of the surfaces having a first end and a second end, a first layer overlying the bottom surface of the substrate having a first opening in alignment with the first end of the lead and a second opening spaced therefrom in alignment with an opening in the substrate extending between the top and bottom surfaces, the first opening operative for receiving a test probe therein for engagement with the first end of the lead for electrical connection to one of the contacts on the microelectronic element upon engagement therewith by the second end of the lead, the second opening operative for receiving a test probe therein for engagement with another one of the contacts on the microelectronic element.
In accordance with another embodiment of the present invention there is disclosed an interposer for testing a microelectronic element having a plurality of contacts. The interposer is arranged in a first and second matrix having different pitch densities, the interposer includes a substrate having a top surface and a bottom surface, a plurality of first openings extending through the substrate arranged in a matrix having a pitch density corresponding to the pitch density of the first matrix of the contacts, the first openings operative for receiving a plurality of test probes for engagement with a corresponding plurality of contacts on the microelectronic element, a plurality of conductive leads on one of the surfaces of the substrate, each lead having a first end and a second end, the second ends of the leads arranged in a matrix having a pitch density greater than the pitch density of the plurality of contacts within the first matrix, the second ends of the leads operative for engagement with the contacts on the microelectronic element arranged in a matrix having a pitch density corresponding to the pitch density of the second matrix of the contacts, a rigid layer overlying the bottom surface of the substrate and having a plurality of second openings in alignment with the first ends of the leads, the second openings operative for receiving a plurality of test probes for engagement with the first ends of the leads for electrical connection to the contacts in the second matrix on the microelectronic element, the rigid layer including a plurality of third openings in alignment with the plurality of the first openings within the substrate, the third openings operative for receiving a plurality of test probes therein for engagement with the contacts in the first matrix on the microelectronic element.
REFERENCES:
patent: 3654585 (1972-04-01), Wickersham
patent: 4551673 (1985-11-01), Barth et al.
patent: 4649338 (1987-03-01
Karlsen Ernest
Lerner David Littenberg Krumholz & Mentlik LLP
Tessera Inc.
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