Apparatus for electrically planarizing semiconductor wafers

Details Apparatus for electrically planarizing semiconductor wafers Apparatus for electrically planarizing semiconductor wafers

2002-07-29

2004-06-29

Picardat, Kevin M. (Department: 2822)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S626000, C438S692000, C438S645000, C438S631000, C205S640000, C205S645000, C205S652000, C205S654000

Reexamination Certificate

active

06756307

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to apparatus and methods for surface planarization of metal surfaces. More specifically, it relates to electropolishing technology for planarizing metal surfaces.
BACKGROUND OF THE INVENTION
In the fabrication of integrated circuits, as the number of levels in an interconnect technology is increased, the stacking of additional layers on top of one another produces a more and more rugged topography. Compounding this problem, electroplating bath additives are now more commonly utilized to aid in the rapid “bottom-up” filling of higher aspect ratio features (e.g. in Damascene copper electroplating processes) to ensure homogeneous metal fill of narrow features. Baths with “bottom-up” filling characteristics fill smaller features much more rapidly than baths without such additives. In some cases (e.g. plating baths with superior bottom-up filling characteristic and no leveling additives) plating occurs at an accelerated rate after completing the small feature filling stage. When many high aspect ratio features are located in close proximity, a macroscopic raised area (series of bumps or a raised plateau) can be formed. This bump formation is also termed, “feature overplating.”
Thus, use of advanced “bottom up” electrofill paradigms in combination with wafers having many low and high aspect features have created a problem of deposited metal surfaces having a range of topography to be planarized that is unusually large, i.e. containing both recessed and raised areas. Commonly, features that vary in size by two orders of magnitude on a single layer exist. A 1 &mgr;m deep feature can have widths of from 0.2 &mgr;m to 100 &mgr;m. Therefore, while electroplating is a preferred method of metalization, various aspects of improved plating regimens create challenging topography for subsequent planarization. Without planarization, the microscopic canyons that result on the integrated circuit surface from stacking of device features create a topography that (1) would limit the resolution of photo-lithography and creation of dense feature patterns, and (2) would lead to defects in the integrated circuit that would make the circuit unusable.
One method of planarization used in the art is chemical mechanical polishing (CMP). CMP is a process that uses a mixture of abrasives and pads to polish the surface of the integrated circuit. Unfortunately, CMP polishing techniques are difficult to control; the endpoint can be difficult to detect. They are also expensive. The high equipment cost, waste handling cost, and low throughput contribute to the overall expense of CMP. Also, with the introduction of low-k dielectrics into chip production, modification of traditional CMP processes will be required, as current methods result in cracking and delamination of most low-k materials, which have a very low compression strength, and are extremely fragile.
Another method of planarization involves electrolytic etching technique such as electropolishing or electroless etching. These techniques are low cost methods, relative to CMP. Lower capital cost, easier waste handling, and much higher processing rates make them desirable alternatives to CMP. Electropolishing is a method of polishing metal surfaces by applying an electric current through an electrolytic bath, and removing metal via electrolytic dissolution. The process may be viewed as the reverse of electroplating.
A problem arises during the electropolishing of surfaces in which a large number of low aspect ratio (larger width than depth) features exist. Wide interconnect lines (trenches cut in a dielectric layer for a damascene process) and contact/bond pads often have low aspect ratios. Low aspect ratio features generally require the plating of an overburden layer slightly thicker than the thickness of the Damascene layer so that the feature will be completely filled after planarization. The metal fill profile above these features exhibits large recesses having profiles which resemble the original (low aspect ratio) feature. The metallization processes used to deposit the metal, which are substantially conformal over such low aspect ratio features, are typically not continued to a point which would geometrically “close” such recesses, because to do so would require depositing a very thick metal layer. To do so would be uneconomical due to necessary removal of the large excess of metal at a later stage. Conventional electropolishing techniques can planarize a surface in which the recessed feature to be planarized is no more than perhaps three times as wide as it is deep. For features wider than these, the rate of removal is essentially uniform everywhere. When the metal layer is electropolished to the dielectric surface, recesses over low aspect ratio features are propagated and expanded to produce recesses that span the width of these features leaving effectively little or no metal in the pad regions. Obviously, this is an unacceptable result.
Reid (U.S. patent application Ser. No. 09/758,307 filed Jan. 9, 2001) describes a method of electrochemical planarization of metal surfaces in which planarization rates are modulated by tight control of the distance between a metal layer to be planarized and a planar cathode (in conjunction with a highly resistive electrolyte). Mayer et al. (U.S. patent application Ser. No. 09/412,837, filed Oct. 5, 1999) describe a method of planarization of metal layers in which a “pad” is used to create localized fluid agitation (and/or physical contact) in raised regions relative to recessed regions to facilitate planarization. Although these inventions address the need for improved electroplanarization in semiconductor fabrication, with the demand for increasingly smaller device features, additional methods and apparatus for metal planarization would be desirable. In particular, it would be desirable to have methods and apparatus that more specifically address non-uniform electropolishing in localized areas of a wafer relative to global planarization.
What is needed therefore is improved electropolishing technology for planarizing conductive layers having varying topography, particularly metal layers having both recesses and raised regions having both very narrow (submicron) and very wide (on the order of 100 micron) widths.
SUMMARY OF THE INVENTION
The present invention pertains to apparatus and methods for electroplanarization of metal surfaces having both recessed and raised features, over a large range of feature sizes. The invention accomplishes this by use of a “reclaim cathode” together with a flexible planar cathode and a spacing pad thereon. During electroplanarization, the flexible planar cathode conforms to the global contour of the work piece (e.g. a wafer) while the spacingpad conforms to local topography of the metal layer being planarized. In this way, dishing is reduced in the final planarized metal layer. The reclaim cathode serves as a counter electrode to the metal workpiece (anode). Therefore, most of the cathodic Faradaic reaction takes place at the reclaim electrode. To a lesser degree, the flexible cathode may undergo some Faradaic reaction.
One aspect of the invention is an electroplanarizing apparatus for removing a portion of a metal layer disposed on a wafer work surface. Such apparatus may be characterized by the following features: a wafer holder for holding the wafer such that the metal layer is exposed, the wafer holder configured to supply an anodic electrical current to the metal layer; a flexible planar cathode having a spacing pad on its surface; a movement assembly configured to position the wafer work surface and the flexible planar cathode into close proximity with each other, whereby at least a pre-defined separation distance between the flexible planar cathode and wafer work surface can be maintained throughout an electroplanarization process; an electrolyte delivery mechanism configured to provide an electrolyte to the spacing pad while the wafer is in contact with the spacing pad; and a mechanism for applying a substantially uniform

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