Apparatus for efficient instruction execution via variable issue

Details Apparatus for efficient instruction execution via variable issue Apparatus for efficient instruction execution via variable issue

1996-05-23

1998-10-13

Lall, Parshotam S.

395384, G06F 938

Patent

active

058225609

ABSTRACT:
An apparatus employs a flexible instruction categorization scheme which includes three categories: single dispatch, multiple dispatch, and microcode. Single dispatch instructions are performed in one functional unit. Conversely, multiple dispatch instructions are conveyed to multiple functional units, each of which perform a portion of the multiple dispatch instruction. A predefined fixed number of functional units are employed to execute a multiple dispatch instruction, allowing for additional instructions to be dispatched concurrently with the multiple dispatch instructions. In contrast to multiple dispatch instructions, microcode instructions may occupy a variable number of functional units and may dispatch instructions for a variable number of clock cycles. Additionally, multiple instruction operations may be performed in a given functional unit in response to an instruction. In one embodiment, up to two instruction operations may be performed in a functional unit. The instruction operations corresponding to a particular instruction are stored as control vectors in a control vector storage within the corresponding functional unit.

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