Apparatus for driving liquid crystal display

Details Apparatus for driving liquid crystal display Apparatus for driving liquid crystal display

1999-12-21

2004-01-20

Shalwala, Bipin (Department: 2673)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S100000

Reexamination Certificate

active

06680720

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a liquid crystal display device, and more particularly, to an apparatus for driving a liquid crystal panel to display a uniform luminance in an entire display area of the liquid crystal panel.
2. Description of the Related Art
Conventionally, a liquid crystal display device (hereinafter LCD) includes a liquid crystal panel and a drive circuit for driving the liquid crystal panel. The liquid crystal panel includes a plurality of liquid crystal cells arranged between two glass-like substrates (e.g., an upper glass substrate and a lower glass substrate), and switching elements (e.g., a thin film transistor (hereinafter TFT) array). The drive circuit is typically provided with gate driving integrated circuits (hereinafter “gate D-IC”) and data driving integrated circuits (hereinafter “data D-IC”).
In a liquid crystal panel, included circuitry uses a system of storage on gate, as shown in FIG.
1
. The circuitry of
FIG. 1
includes picture elements (or pixels) that are arranged at intersections of gate lines GL
1
to GLn and data lines DL
1
to DLm, respectively. Each of the picture elements includes a TFT (MN
11
to MNnm) having a gate terminal connected with the gate line GL, a source terminal connected with the: data line DL, a liquid crystal cell (CLC
11
to CLCnm) connected between the drain terminal of the TFT and a common voltage line VCL, and an additional capacitor (Cst
11
to Cstnm) connected to the drain terminal of the TFT. The additional capacitors Cst
21
to Cstnm arranged on the second to nth gate lines GL
2
to GLn are also connected to the corresponding previous gate lines GL
1
to GLn−1, respectively, whereas the additional capacitors Cst
11
to Cst
1
m
on the first gate line GL
1
are connected to a storage line SL. Each data line DL
1
to DLm receives a video signal from a data D-IC, and each gate line GL
1
to GLn inputs a gate signal (GS
1
to GSn) from a gate D-IC.
Data lines DL
1
to DLm are driven using the dot inversion system. In the dot inversion system, a video signal on one data line DLi has a polarity that is opposite to that of the video signals on data lines DLi−1 and DLi+1, both of which are adjacent to data line DLi. The TFTs MN are selectively turned-on by the gate signal having a pulse shape in order to transmit the video signals on the data lines DL
1
to DLm to the liquid crystal cells CLC and the additional capacitors Cst. Then, the liquid crystal cells CLC and the additional capacitors Cst charge the video signal applied from the data line DL through the TFT MN, and maintain the charged signal voltage until the TFTs are turned-on again (i.e., during turning-off of the TFTs). Storage line SL is used as a storage capacitor of the picture elements connected to first gate line GL
1
. Similarly, the first to (n−1)th gate lines GL
1
to GLN−1 are used as the storage capacitor of the picture elements on the second to nth gate lines GL
2
to GLn, respectively.
Referring to
FIG. 2
, a storage signal SS applied to the storage line SL has a direct current voltage maintaining a constant voltage level (e.g., −5V). It is possible to set the voltage level of the storage signal SS equal to the low voltage level of the gate signal GS. Also, gate lines GL
1
to GLn receive pulse-shaped gate signals GS
1
to GSn, which have trailing edges that gradually descend. This is caused by the gate signal GS being delayed by an output buffer (snot shown) and wiring included in the gare D-IC if a high voltage and a low voltage of the gate signal GS are 20V and −5V. respectively, the trailing edge of the gate signal GS consumes about a few milliseconds. More specifically, the trailing esge of the gate signal falls from the voltage level of 20V to the voltage level of −4.96V within several microseconds, and then from the voltage level of −4.96V to the voltage level of −5V in period of a few milliseconds. Because the storage signal SS on the storage line SL maintains a constant voltage level, and because each gate signal GS
1
to GSn does not maintain a constant voltage level, esch pixel voltage charged at each picture element on the first gate line GL
1
is different from each pixel voltage charged at each picture element on the rest of the gate lines GL
2
to GLn.
Such a pixel voltage difference between the gate lines GL
1
to GLn will be described in reference to
FIGS. 3A and 3B
.
FIG. 3A
shows a waveform of pixel voltage VS
1
charged at the picture element on the first gate line GL
1
, and
FIG. 3B
represents a waveform of pixel voltage VS
2
charged at each picture element on the rest of the gate lines (i.e., the second to last gate lines GL
2
to GLn). Referring to
FIGS. 3A and 3B
, a predetermined level of voltage difference is generated between the pixel voltage VS
1
charged at the picture element on first gate line GS
1
and the pixel voltage VS
2
charged at each pixel on the rest of the gate lines GL
2
to GLn, although the data signals having the same voltage are applied to all of the lines. For example, if the data signal to be applied to each picture element on the first gate line GL
1
and the rest of the gate lines GL
2
to GLn is 5V when the common voltage is fixed at 3V, +2V is the charge at each picture element on the first gate line GL
1
and each picture element on the rest of the gate lines GL
2
to GLn at first. However, the storage voltage at the picture element on the first gate line GL
1
maintains the voltage level of −5V after the TFT on the first gate line GL
1
is turned off, while the storage voltage at each picture element on the rest of the gate lines GL
2
to GLn has the voltage level of −4.96V at the moment when the TFTs on the rest of the gate lines GL
2
to GLn are turned off. The storage voltage at each picture element on the rest of the gate lines GL
2
to GLn decreases gradually and drops down to −5V after several milliseconds from the moment when the TFTs on the rest of the gate lines GL
2
to GLn are turned off. Since the storage voltage drops down when the TFTs are turned off, the voltage VS
2
charged at each picture element on the rest of the gate lines GL
2
to GLn also drops by a capacitor coupling effect. If this voltage drop is represented by &Dgr;V, there exists a voltage difference of &Dgr;V between the picture elements on the first and second gate lines GL
2
and GL
2
. The voltage difference &Dgr;V in the above example can be calculated as shown in equation 1 below.
&Dgr;
V=[C
st
·(−4.96−(−5.0))]/(
C
LC
+C
st
+C
gs
)  (1)
In the above equation, “C
LC
” and “C
st
” are the capacitance of the liquid crystal cell C
LC
and the capacitance of the storage capacitors C
st
, respectively, and “C
gs
” represents a parasitic capacitance between the gate and source terminals of TFT MN. The different voltage &Dgr;V is below 40 mV in the above case. Due to the different voltage &Dgr;V between the first pixel voltage(VS
1
) on each picture element of the first gate line GL
1
and the second pixel voltage(VS
2
) on each picture element of the second to nth gate lines, the luminance level on a first line of the liquid crystal panel is different from that of the rest of the lines of the liquid crystal panel.
SUMMARY OF THE INVENTION
To overcome the problems described above, preferred embodiments of the present invention provide a liquid crystal panel drive apparatus that displays a uniform luminance level on the entire liquid crystal panel.
A liquid crystal panel drive apparatus according to one preferred embodiment of the present invention applies an alternative current signal to a storage line on the liquid crystal panel.
A liquid crystal panel drive apparatus according to another preferred embodiment of the present invention includes a connector connecting a storage line on a liquid crystal panel with a gate line among a plurality of the gate lines on the liquid crystal panel.
A liquid crystal panel drive appar

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