Apparatus for distortion free clearing of a display during a sin

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Details

364521, 340747, 340750, 340799, 340814, G06F 1562, G09G 116

Patent

active

047018631

ABSTRACT:
A graphics display is cleared by apparatus forcing binary ZERO's into all locations of the bit map memories between successive vertical synchronization operations during a write refresh operation.

REFERENCES:
patent: 4016544 (1977-04-01), Morita et al.
patent: 4143360 (1979-03-01), Bernhart et al.
patent: 4270125 (1981-05-01), Weisbecker
patent: 4342029 (1982-07-01), Hofmanis et al.

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