Apparatus for developing an address of a segment within main mem

Communications: electrical – Digital comparator systems

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G06F 900

Patent

active

039380963

ABSTRACT:
Computer addressing hardware and a method of address development which utilizes the concept of a segment as the unit of addressability is disclosed.
The fundamental vehicle for addressing is the segment wherein an address space is defined for a process and is included as part of the controlled information of the logical processor (the collection of hardware resources and control information necessary for the execution of a process.) The address space defines a predetermined number of different segments in which instructions can access operands. Within a segment, access is by relative location to the beginning of the segment, and is computed during address development. Any attempt to access information beyond the upper bound of the segment is detected by hardware and an exception condition occurs. An instruction may access an operand either directly or indirectly via a data descriptor, wherein an address syllable in the instruction is used for reference, and specifies whether reference is direct or indirection is to be preferred. The address syllable specifies a base register which defines the segment to be referenced and an offset within the segment. The address syllable also contains a displacement from this defined base. Address development hardware obtains the absolute address of the beginning of the segment, adds to this; the offset defined in the base registers, the displacement defined by the instructions, and if required the contents of an index register. This summation produces the required absolute address.

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patent: 3731283 (1973-05-01), Carlson et al.
patent: 3764996 (1973-10-01), Ross
patent: 3800286 (1974-03-01), Brown et al.

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