Boots – shoes – and leggings
Patent
1990-06-07
1992-12-29
Dixon, Joseph L.
Boots, shoes, and leggings
364DIG1, 364DIG2, 3408255, 34082552, G06F 1300, G06F 1316, G06F 1200, G06F 1204
Patent
active
051758334
ABSTRACT:
A cache memory which includes a cache controller formed on a single substrate. A plurality of the identical memories may be used in an array. The memories themselves determined how many other memories are in an array and each of their relative positions in the array. From this information, each memory sets the range of its set fields and the size of its tag fields. This is done on reset with the configuration information being distributed among the memories themselves, without being centrally stored, and in a manner transparent to the software.
REFERENCES:
patent: 4360870 (1982-11-01), McVey
patent: 4468729 (1984-08-01), Schwartz
patent: 4951248 (1990-08-01), Lynch
patent: 4964038 (1990-10-01), Louis et al.
Netzer Zvi
Yarkoni Eran
Dixon Joseph L.
Intel Corporation
Leibold Gregory D.
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