Apparatus for determining cacheability of a memory address to pr

Details Apparatus for determining cacheability of a memory address to pr Apparatus for determining cacheability of a memory address to pr

1990-12-05

1993-09-21

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642434, G06F 1208, G06F 1314

Patent

active

052476421

ABSTRACT:
A computer system includes an Intel 80486 microprocessor having an internal cache memory and a local memory tightly coupled to the microprocessor that can respond to memory accesses without requiring the microprocessor to execute a wait state. An external cache memory system is provided to provide additional cache storage to provide copy back capabilities so that data written to the external cache does not have to be automatically written to slower bulk memory. The computer system includes a conventional Industry Standard Architecture bus (ISA-bus) which may include memory on the bus. The computer system may also include an external math coprocessor. In order to preclude storing data from the math coprocessor and from the ISA-bus memory, the external cache memory system includes a cache determination circuit that selectively generates a cache enable signal to the microprocessor and to the external cache memory system so that only cacheable data is stored in the two caches. The cache determination circuit operates sufficiently fast that when the microprocessor addresses a zero-wait state device, such as the external math coprocessor or the local memory, a cache enable signal is generated within the first clock cycle so that the local memory can respond within the second clock cycle without requiring a microprocessor wait state and the cache enable signal is not generated if the math coprocessor is addressed.

REFERENCES:
patent: 4669043 (1987-05-01), Kaplinsky
patent: 4819154 (1989-04-01), Stiffler et al.
patent: 5045998 (1991-09-01), Begun et al.
patent: 5091846 (1992-02-01), Sachs et al.
patent: 5091850 (1992-02-01), Culley
patent: 5097532 (1992-03-01), Borup et al.
patent: 5109334 (1992-04-01), Kamuro
patent: 5155834 (1992-10-01), Ryan et al.
M. Morris Mano, Computer System Architecture, 2nd edition, pp. 403-473.
Cliff Rhodes, "Caches keep main memories from slowing down fast CPUs," Electronic Design, Jan. 21, 1982, pp. 179-184.
Cliff Rhodes, et al., "Cache-memory functions surface on VLSI chip," Electronic Design, Feb. 18, 1982, pp. 159-163.
Jerry VanAken, "Match cache architecture to the computer system," Electronic Design, Mar. 4, 1982, pp. 93-95, 97, 98.
Efrem G. Mallach, "What does cache buy for you?", Mini-Micro Systems, May 1982, pp. 267, 268, 271.
Robert Hartwig, et al., "Large disk cache uses fast 64k-by-1 static RAMs to speed data-base accesses," Electronic Design, Sep. 19, 1985, pp. 193-198, 200, 202.
Howard Sachs, "Improved Cache Scheme Boosts System Performance," Computer Design, Nov. 1, 1985, pp. 83-86.
Alan Jay Smith, "Cache memory design: an evolving art," IEEE Spectrum, Dec. 1987, pp. 40-44.
David Shear, "Cache-memory systems benefit from on-chip solutions," EDN, Dec. 10, 1987, 245-249, 252, 253, 258, 260.
William Ringer, "How to Manage Your Cache Options," ESD: The Electronic System Design Magazine, Jun. 1988, pp. 71, 72, 74, 75.
Jim Langston, "Boost DRAM performance with SRAM caching scheme," Electronic Design, Jun. 9, 1988, pp. 107-112.
Richard Crisp, et al., "Designing A Cache for a Fast Processor," Electronic Design, Oct. 13, 1988, pp. 111-116, 118.
Mark D. Hill, "A Case for Direct-Mapped Caches," Computer, Dec. 1988, pp. 25-40.
Mammad Safai, "Cache Design Paces 33-MHz 80386 CPUs," Microprocessor Design Guide, 1989, pp. 39, 42, 44, 46, 48.
Joseph C. Circello, et al., "Refined method brings precision to performance analysis," Computer Design, Mar. 1, 1989, pp. 77-80, 82.
Jim Peterson, "System-Level Concerns Set Performance Gains," High Performance Systems, Sep. 1989, pp. 71-73, 76, 77.
Raymond M. Leong, "Cache memories and MMUs work together in high-speed systems," EDN, Mar. 15, 1990, pp. 169-172, 174.

Affiliated with

Also associated with

Rating

Apparatus for determining cacheability of a memory address to pr does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for determining cacheability of a memory address to pr, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for determining cacheability of a memory address to pr will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1057027