Apparatus for determining booth recoder input control signals

Details Apparatus for determining booth recoder input control signals Apparatus for determining booth recoder input control signals

1991-10-11

1994-01-18

Nguyen, Long T.

Boots, shoes, and leggings

G06F 752

Patent

active

052804399

ABSTRACT:
In an apparatus and method for computing inverses and square roots, a highly accurate initial approximation is computed using a second order polynomial equation, the coefficients of which are stored in a ROM. The most significant bits of an operand are used to address a ROM to select coefficients, providing different coefficients for different operand ranges. The remaining lesser significant operand bits are used in the computation; the coefficient values already account for the bits used to address them. The result is in single precision accuracy. For double precision, the polynomial results are used as the first approximation for a Newton-Raphson iteration. The multiplier has a split array mode to speed up the calculation of the polynomial, whereby two lesser precision values can be computed at once. The size of the coefficients is tailored to produce the proper precision result for each of the elements of Ax.sup.2 +Bx+C. Separate values for the coefficients A, B, and C must be stored for the 1/x approximation and for the 1/.sqroot.x approximation. Also to speed up the multiplier, the multiplier can accept one operand in carry/save format, by providing Booth recoder logic which can accept operands in a normal binary or in a carry/save format. Also employed is a rounding technique which provides IEEE exact rounding by an operation that includes only one multiplication.

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D. Steiss et al., "A 65MHz Floating-Point Coprocessor . . . ," IEEE, 1991, pp. 94 and 95.
"IEEE Standard for Binary Floating-Point Arithmetic," IEEE, 1985, pp. 7-18.
Article entitled "Performing Floating Point Division . . . ," Weitek Corporation.
S. Waser et al., "Introduction to Arithmetic for Digital . . . ," CBS College Publishing, New York, 1982, pp. 196-199.
Hennessy & Patterson, "Computer Architecture," Morgan Kaufmann Publishers, Inc., 1990, pp. A23 to A26, A63 to A66.

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