Apparatus for detecting updates to instructions which are within

Details Apparatus for detecting updates to instructions which are within Apparatus for detecting updates to instructions which are within

1996-02-14

1998-04-21

Kim, Matthew M.

395381, 395467, 395403, G06F 1208, G06F 938

Patent

active

057427917

ABSTRACT:
A core snoop buffer apparatus is provide which stores addresses of pages from which instructions have been fetched but not yet retired (i.e. the instructions are outstanding within the instruction processing pipeline). Addresses corresponding to memory locations being modified are compared to the addresses stored in the core snoop buffer on a page basis. If a match is detected, then instructions are flushed from the instruction processing pipeline and refetched. In this manner, the instructions executed to the point of modifying registers or memory are correct in self-modifying code or multiprocessor environments. Instructions may be speculatively fetched and executed while retaining coherency with respect to changes to memory. The number of pages from which instructions are concurrently outstanding within the microprocessor are typically small compared to the number of cache lines outstanding or the number of instructions outstanding. Therefore, a relatively small hardware structure may be employed to perform the instruction coherency functionality.

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