Apparatus for detecting undefined states of a finite state machi

Details Apparatus for detecting undefined states of a finite state machi Apparatus for detecting undefined states of a finite state machi

1993-04-05

1996-06-11

Lee, Thomas C.

Boots, shoes, and leggings

364DIG1, 364265, 3642656, 3642664, 39518501, 371 571, G06F 1130

Patent

active

055264867

ABSTRACT:
A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.

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IBM Technical Disclosure Bulletin, vol. 21, No. 5, Oct. 1978, New York, U.S. p. 2022, Beaven et al. "Verification That A Logic Design Does Not Enter An Illegal State."
Section EI, Week E05, 17 Mar. 1982, Derwent Publications Ltd., London, GB; Class T, An B2238E and SU-826 356, Mazurenko.
Derwent Research Disclosure, RD 290074, 10 Jun. 1988, DW8831, An 88-218147; Anonymous: "Finite State Machine for CKD Execution by Control Unit--Starts in State 1 and Proceeds to Different States Depending Upon Received CCW."

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