Apparatus for detecting possibility of parallel processing and m

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3649468, 364973, 3642804, 3642621, G06F 945, G06F 9455

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active

054505542

ABSTRACT:
The present invention provides an apparatus for detecting whether a program having an iterative loop can be processed in parallel. The apparatus includes including a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing values of variables that are defined by program statements executed during simulation of the iterations, each stored variable being stored with information showing a location in the program where the value of the variable is defined and the simulated iteration number during which the variable is defined, and a judgement unit for judging that parallel processing is possible when, for each simulated iteration, variables appearing undefined in any program statements of that iteration are defined in preceding program statements within that iteration. The present invention further provides a program translation apparatus for generating a program applicable to parallel processing if a possibility of executing the program in parallel is detected. The program translation apparatus includes the simulation unit, the variable storage unit, the judgement unit, and program generation circuitry for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

REFERENCES:
patent: 4833606 (1989-05-01), Iwasawa
patent: 5067068 (1991-11-01), Iwasawa
patent: 5151991 (1992-09-01), Iwasawa
patent: 5230053 (1993-07-01), Zaiki
patent: 5317743 (1994-05-01), Imai
Advanced Compiler Optimizations for Supercomputers, David A. Padua et al, Communications of the ACM, Special Issue, Dec. 1986, vol. 29, No. 12.

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