Apparatus for detecting parity errors among asynchronous digital

Details Apparatus for detecting parity errors among asynchronous digital Apparatus for detecting parity errors among asynchronous digital

1992-06-11

1995-02-21

Beausoliel, Jr., Robert W.

Excavating

371 571, 371 491, G06F 1106, H03M 1300

Patent

active

053924240

ABSTRACT:
A communication circuit sends asynchronous digital signals in parallel to an external device. A first parity circuit in the communication circuit computes a first bit which indicates the parity of the control signals. This first bit is sent to the external device. When the digital signals and the parity bit are received by the external device, a first control signal is produced when each of the received digital signals has the same logic level for a defined period of time. A second parity circuit produces a second control signal when a parity error is found in the received digital signals. An error signal is generated in response to the presence of both the first and second control signals.

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