Boots – shoes – and leggings
Patent
1988-02-11
1990-08-14
Shaw, Gareth D.
Boots, shoes, and leggings
3642466, 3642615, 3642428, 36424291, G06F 1214
Patent
active
049492381
ABSTRACT:
To detect a memory protection violation at high speed in a data processor for executing microinstructions, plural memory protection information of a descriptor of a new segment program are simultaneously discriminated true or false on the basis of current privilege level and branch condition information of a memory protection branch microinstruction. If discriminated true, the succeeding microinstruction is selected. If false, the current microinstruction is branched to a designated branch address included in the branch microinstruction. The apparatus comprises, an attribute information register for storing plural memory protection information of a new decriptor; a current privilege level register; a privilege level comparator; a microinstruction register for storing a memory protection branch microinstruction including plural branch condition information and a branch address; a memory protection violation detector having AND gates, inverters, and an OR gate; and a read address selector having an adder, etc.
REFERENCES:
patent: 3909802 (1975-09-01), Cassarino, Jr. et al.
patent: 4754393 (1988-06-01), Kitson et al.
patent: 4763245 (1988-08-01), Emma et al.
Eakman Christina M.
Kabushiki Kaisha Toshiba
Shaw Gareth D.
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