Pulse or digital communications – Miscellaneous
Reexamination Certificate
1997-09-09
2001-05-08
Pham, Chi (Department: 2631)
Pulse or digital communications
Miscellaneous
C714S758000
Reexamination Certificate
active
06229866
ABSTRACT:
This application claims the benefit of Korean Application Number 8320/1997 filed on Mar. 12, 1997, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an asynchronous data receiver and transmitter, and more particularly, to an apparatus for detecting errors in an asynchronous data receiver and transmitter.
2. Discussion of the Related Art
Most of modules for general system construction employ a central processing unit (CPU) for processing data. There are two methods for transmitting and receiving data between modules. One of the methods is the synchronous method in which data processing clocks are synchronized with data receiving and transmission operations between modules. The other method is the asynchronous method in which data is processed asynchronously.
In the synchronous method, many additional circuits are required in the system in order to provide suitable synchronization between the modules. This decreases the data processing rate of the system.
In contrast, in the asynchronous method, each of the reading module and the writing module employs an input/output buffer. Thus, a good data-processing rate and economical cost can be achieved.
A conventional apparatus for detecting errors in an asynchronous data receiver and transmitter will be described with reference to the accompanying drawings.
FIG. 1
is a block diagram showing a conventional apparatus for detecting errors in an universal asynchronous receiver and transmitter (UART), and
FIG. 2
shows one frame of a conventional UART.
Referring to
FIG. 1
, an apparatus for detecting errors in an UART
10
includes a sample block
11
for sampling values of serial data received by the UART
10
, a parity check block
12
for checking the values of the data sampled by the sample block
11
and comparing the values with parity to detect errors, a line control resister
13
for designating the length and the value of a parity bit to be detected by the sample block
11
and the parity check block
12
, and a buffer register
14
for storing the data checked by the parity check block
12
.
For example, the operation of the UART having the aforementioned structure is determined as an error if the number of ‘1’ of a data parity is even. The operation is deemed to be normal if the number of ‘1’ of a data parity is odd.
In the error detecting apparatus of an UART, a parity desired to be detected is designated using the line control register
13
. The parity of the serial data received by using the designated parity is calculated by one bit in the sample block
11
.
If the parity bit and the value calculated in the sample block
11
are not identical when the value calculated in the sample block
11
is compared with a parity bit next received in the parity check block
12
, a parity error is detected. For example, if an even parity detection is designated in the line control register
13
and a received serial data is 00101000, the parity bit is ‘0’. If, compared with a parity bit received next, this value is not identical with the parity bit, a message of parity error is recorded in a line status register (not shown) and interruption of the operation is requested.
FIG. 2
shows an UART frame including a start bit, a data bit, a parity bit, and a stop bit. When the UART frame receives a serial data signal, the sample block
11
samples serial data values by bits. After required data is stored in the buffer register
14
for a predetermined time, the data is transmitted or received.
The conventional apparatus for detecting errors in an UART is not capable of precisely detecting errors. As a result, the UART receives incorrect data. For example, if a data of 00101010 is sent by a remote system such that a local system has sampled a data of 00110010, a parity error will not be generated. As a result, a wrong data is transmitted and received.
SUMMERY OF THE INVENTION
Accordingly, the present invention is directed to an apparatus for detecting errors in an asynchronous data receiver and transmitter that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide an apparatus for detecting errors in an asynchronous data receiver and transmitter suitable for precisely and rapidly detecting errors when receiving and transmitting data.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the apparatus for detecting errors in an asynchronous data receiver and transmitter includes a first sample block for first sampling received data, a first storing part for storing a value of the data sampled by the first sample block for a predetermined time, a second sample block for secondly sampling the received data, a second storing part for a value of the data sampled by the second sample block for a predetermined time, and a comparing part for receiving and comparing the values of the data stored in the first and second storing parts and outputting an error signal if the values of the data are not identical.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4736189 (1988-04-01), Katsumata et al.
patent: 5056115 (1991-10-01), Meuriche
patent: 5488639 (1996-01-01), MacWilliams et al.
patent: 5530483 (1996-06-01), Cooper et al.
patent: 5539298 (1996-07-01), Perkins et al.
patent: 5598429 (1997-01-01), Marshall
patent: 5608514 (1997-03-01), Stann et al.
patent: 5815101 (1998-09-01), Fonte
National Semiconductor Co., PC 16550D Data Book (Jun. 1995).
Corrielus Jean B.
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
Pham Chi
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