Boots – shoes – and leggings
Patent
1993-12-14
1995-06-06
Bowler, Alyssa H.
Boots, shoes, and leggings
3642295, 3642387, 364240, 36424291, 36424341, 3642467, 3642465, 3642522, 3642554, 3642557, 3642558, 3642584, 364259, 3642592, 3642602, 3642633, 364DIG1, 364DIG2, G06F 702, G06F 926, G06F 9345, G06F 1110
Patent
active
054228379
ABSTRACT:
In order to validate data manipulation results in a CPU which incorporates duplicate BPUs for integrity, which BPUs are typically each implemented on a single VLSI circuit chip, and which is capable of performing single and double precision data manipulation operations, two cache units are employed. Each cache unit is dedicated to handling half-bytes of information and incorporates highly reliable data validating logic without the necessity for providing double word wide output busses from each BPU. This feature, which lowers the lead count to each VLSI chip, is obtained by dedicating each cache unit to handling half-bytes of information. Each cache unit includes bit-by-bit comparison circuitry to validate the half-byte results received from both BPUs in the case of single precision operations, and, in the case of double precision operation, one cache unit employs the same bit-by-bit comparison circuitry to validate, for both cache units, the result parity bits, and hence the half-byte results, received from both BPUs.
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Boothroyd Donald C.
Flocken Bruce E.
Inoshita Minoru
Bowler Alyssa H.
Bull HN Information Systems Inc.
Pan Daniel H.
Phillips J. H.
Solakian J. S.
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