Apparatus for detecting any single bit error, detecting any two

Details Apparatus for detecting any single bit error, detecting any two Apparatus for detecting any single bit error, detecting any two

1992-07-22

1996-02-13

Beausoliel, Jr., Robert W.

Excavating

371 377, 371 381, 371 391, 371 493, H03M 1300

Patent

active

054917026

ABSTRACT:
An error detection system wherein 64 bits of data word are protected by 8 check bits which yield 8-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1"s or by syndromes that contain exactly five "1"s in which bits 0-3 or 4-7 of the syndrome are all "1." Single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1." All two-bit errors, and four-bit errors within a nibble, are indicated by syndromes that contain an even number of "1"s (i.e., an even number of "1"s). Three-bit errors within a nibble are indicated by syndromes that contain five "1"s in which bits 0-3 of the syndrome and bits 4-7 of the syndrome are not all "1." Four-bit errors within a nibble are indicated by syndromes that contain four "1"s. In another embodiment of the invention, 25 bits of data word are protected by 7 check bits yielding 7-bit syndromes. Single-bit errors are indicated by syndromes that contain exactly three "1" s except single-bit errors that occur from faulty check bits are indicated by syndromes that contain exactly one "1". Two-bit errors are indicated by syndromes that contain an even number of "1"s, and three-bit errors within a nibble are indicated by syndromes that contain five "1"s or seven "1"s. Four-bit errors within a nibble are indicated by syndromes that contain four "1"s or six "1"s.

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