Apparatus for detecting and correcting cyclic redundancy check e

Details Apparatus for detecting and correcting cyclic redundancy check e Apparatus for detecting and correcting cyclic redundancy check e

1996-06-14

1998-05-05

Chung, Phung

Excavating

371 377, 371 671, G06F 1110, H03M 1300

Patent

active

057486522

ABSTRACT:
A cyclic redundancy check (CRC) circuit for detecting and correcting errors in a data stream uses a decoder and a serial-to-parallel buffer to shorten arithmetic operation time. The CRC circuit includes a first gate for switching a serial input data stream into a syndrome register section, and a buffer register for converting the serial input data to a parallel data. The syndrome register section forms redundancies for input data stream. An OR gate receives data from the syndrome register section to enable a decoder if the syndrome register section detects an error in the data stream. The decoder decodes the output from the syndrome register section. The output of the decoder is exclusively-ORed with the input data in the parallel shift register. A latch circuit thereafter outputs a corrected serial data stream.

REFERENCES:
patent: 4679082 (1987-07-01), Shibasaki
patent: 4785468 (1988-11-01), Yoshida
patent: 5251215 (1993-10-01), Dravida et al.
patent: 5473615 (1995-12-01), Boyer et al.

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