Apparatus for delaying the output of data onto a system bus

Details Apparatus for delaying the output of data onto a system bus Apparatus for delaying the output of data onto a system bus

1995-10-03

1998-06-23

Butler, Dennis M.

395559, G06F 104

Patent

active

057713723

ABSTRACT:
Circuitry within a processor delays the launching of data onto an external bus by a factor that is proportional to the ratio of an internal processor clock speed to the system or external bus clock speed. This delay provides a delay in the launching of data to external bus devices so that these slower speed external bus devices have enough time to capture the data.

REFERENCES:
patent: 5600824 (1997-02-01), Williams et al.

Affiliated with

Also associated with

Rating

Apparatus for delaying the output of data onto a system bus does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for delaying the output of data onto a system bus, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for delaying the output of data onto a system bus will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1400647