Apparatus for deferring error detection of multibyte parity enco

Details Apparatus for deferring error detection of multibyte parity enco Apparatus for deferring error detection of multibyte parity enco

1981-03-27

1983-06-14

Springborn, Harvey E.

Boots, shoes, and leggings

371 38, G06F 1110

Patent

active

043886841

ABSTRACT:
Apparatus is included in a main memory subsystem of a data processing system which receives multibyte data from a plurality of input/output devices connected to a common bus. During a write cycle of operation, a device applies the multibyte data signals together with associated parity bits for writing into an addressed storage location of memory. During the write cycle, error encoder circuits generate check code bits from the multibyte data and parity bits which are coded to signal selectively the presence of a multibyte uncorrectable error condition in accordance with the parity bits from a device. During a read cycle of operation, error detection and correction decoder circuits connected to the memory in response to the data and check bits read out from an addressed location are operative to generate a number of syndrome bits. These bits have a predetermined characteristic for indicating the existence of an uncorrectable error condition when one or more data bytes were in error and there was a single bit error in memory.

REFERENCES:
patent: 3579200 (1971-05-01), Davis et al.
patent: 3836957 (1974-09-01), Duke et al.
patent: 3905023 (1975-09-01), Perpiglia
patent: 4072853 (1978-02-01), Barlow et al.
patent: 4355391 (1982-10-01), Alsop
patent: 4358848 (1982-11-01), Patel

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