Apparatus for decoding variable length codes

Coded data generation or conversion – Digital code to digital code converters – To or from variable length codes

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H03M 740

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active

054041384

ABSTRACT:
An apparatus for decoding variable length codes utilizing a parallel processing based on a code classification wherein an address determining logic receives output data from a barrel shifter, determines addresses by groups according to the received data, classifies and designates addresses of a decoder look-up table by groups according to the addresses determined by groups. As a result, a high processing speed can be obtained, over the conventional serial processing system. Moreover, no code deformation is required as in Lukacs system. The memory capacity of the decoder look-up table can be reduced, as compared with the conventional parallel processing method. In addition, the present invention can be applied to decoding of all variable length codes having a prefix structure.

REFERENCES:
patent: 5173695 (1992-12-01), Sun et al.
patent: 5233348 (1993-08-01), Pollman et al.
A. Mukherjee et al., "Efficient VLSI Designs for Data Transformation of Tree-Based Codes," IEEE Transaction on circuit and Systems, pp. 306-314, vol. 38, No. 3, Mar. 1991.
R. Hunter et al., "International Digital Facsmile Coding Standards," Proceedings of IEEE, pp. 854-867, vol. 68, No. 7, Jul. 1980.
U. Hofker et al., "VLC Encoder/Decoder Chip for Digital HDTV Recording," Heinrich-Hertz-Institut fur Nachrichtenchnik Berlin GmbH, Proceedings of International Workshop on HDTV, pp. 45.1-45.4, Nov.18-20, 1992 Kawasaki, Japan.
Y. Yan, "A High Speed Variable Length Decoder for Digital HDTV System," Industrial Technology Research Institute Computer & Communication Research Lab, Proceedings of International Workshop on HDTV, pp. 45.1-45.4, Nov. 18-20, 1992, Kawasaki, Japan.

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