Apparatus for data recovery in a synchronous chip-to-chip...

Pulse or digital communications – Repeaters – Testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C375S360000, C375S362000, C375S375000, C370S517000, C714S731000, C714S744000

Reexamination Certificate

active

06836503

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of signal communications and more particularly to high-speed transfer of information within and between integrated circuit devices using electrical signaling.
BACKGROUND
In modern electronic systems, data and control information are transferred between various subsystems using extremely short-lived electrical signals. For example, in high-speed memory systems, a data signal from a memory controller to a memory device may be valid at the input of the memory device for only a nanosecond or less; less time, in some cases, than the propagation time of the data signal on the signaling path between the memory controller and the memory device. In any such high-speed signaling system, the ability of the receiving device to sample the data signal at a precise instant within the valid data interval (the “data eye”) is often a critical factor in determining how brief the data eye may be and, consequently, the overall data transfer rate of the system. Accordingly, any technique for more accurately controlling the sampling instant within the data eye generally permits faster data transfer and therefore higher signaling bandwidth.
FIG. 1
illustrates a prior art high-speed signaling system in which a strobe signal is transmitted on strobe line DQS to control the sampling of data signals transmitted on data lines, DQ
0
-DQN. Because the strobe signal is edge-aligned with the data signals when transmitted (i.e., the strobe signal transition coincides with the opening of the data eye) and the DQS line introduces nominally the same propagation delay as the DQ
0
-DQn lines, the strobe signal and data signals arrive at the receiving device at nearly the same time. A variable delay circuit
15
then delays the strobe signal by half the nominal duration of the data eye so that the delayed strobe signal transitions at the midpoint of the data eye.
In order to prevent the delayed strobe signal from drifting away from the midpoint of the data eye (e.g., due to changes in voltage and temperature), a delay-locked loop circuit (DLL)
12
is provided to adjust the delay applied by the variable delay circuit over time. A variable delay circuit
21
within the DLL is formed by coarse and fine delay elements that correspond to coarse and fine delay elements within the variable delay circuit
15
in the strobe signal path. As the output of the variable delay circuit
21
within the DLL drifts out of phase with a reference clock signal (e.g., due to changes in voltage and temperature), the phase difference is detected by a phase detector
18
which outputs a signal to a delay control circuit
20
to adjust the delay control value applied to the variable delay circuit
21
. The adjustment to the delay control value results in adjustment in the number of coarse and/or fine delay elements in the signal path of the variable delay circuit
21
so as to drive the output of the variable delay circuit
21
back toward phase lock with the reference clock signal. As shown in
FIG. 1
, the delay control value is also provided, after translation in a ratio circuit
22
according to the ratio between the reference clock period and one half the data eye duration, to the variable delay circuit
15
in the strobe signal path. By this arrangement, the delay applied to the data strobe signal is automatically adjusted to compensate for variations in voltage and temperature. Other relatively constant sources of error (e.g., process variations, mismatches in the DQS and DQ paths, etc.) may be compensated by the initial selection of coarse and fine delay elements within the variable delay circuit
21
.
Unfortunately, because a delayed version of the data strobe signal is ultimately used to control the sampling of the DQ lines (a technique referred to herein as direct strobing), any transient sources of timing error in the data strobe signal such as intersymbol interference (ISI) and cross-talk, or data-dependent timing errors resulting from mismatched rising and falling edge rates are not significantly compensated by the variable delay circuit
15
and instead appear as timing jitter at the sample control inputs of the data receiver. This phenomenon is illustrated in FIG.
2
. As shown, a strobe signal
31
is delayed by an amount of time, T
EYE
/2, to produce a delayed strobe signal
33
that transitions at the midpoint of the data eye. Slightly advanced and delayed versions of the strobe signal
31
resulting from transient sources of timing error are illustrated by dashed lines
34
and
35
, respectively. Because the transient sources of timing error are passed through to the output of the variable delay circuit
15
of
FIG. 1
, the delayed strobe signal
33
is likewise advanced or delayed, resulting in a sampling point that is offset from the ideal sampling point as shown. As discussed above, such inaccuracy in the sampling point translates to lost timing margin and ultimately to reduced data transfer rates.
SUMMARY
In accordance with an aspect of the present invention, an apparatus is disclosed that can reduce sampling errors for data communicated between devices. The apparatus uses phase information acquired from a timing reference signal such as a strobe signal to align a data-sampling signal for sampling a data signal that was sent along with the timing reference signal. The data-sampling signal may be provided by adjustably delaying a clock signal according to the phase information acquired from the strobe signal. The data-sampling signal may also have an improved waveform compared to the timing reference signal, including a fifty-percent duty cycle and sharp transitions. The phase information acquired from the timing reference signal may also be used for other purposes, such as aligning received data with a local clock domain, or transmitting data so that it arrives at a remote device in synchronism with a reference clock signal at the remote device.


REFERENCES:
patent: 4663735 (1987-05-01), Novak et al.
patent: 5485490 (1996-01-01), Leung et al.
patent: 5642386 (1997-06-01), Rocco
patent: 5646968 (1997-07-01), Kovacs et al.
patent: 5838749 (1998-11-01), Casper et al.
patent: 5910740 (1999-06-01), Underwood
patent: 5990968 (1999-11-01), Naka et al.
patent: 6085345 (2000-07-01), Taylor
patent: 6100733 (2000-08-01), Dortu et al.
patent: 6111446 (2000-08-01), Keeth
patent: 6125157 (2000-09-01), Donnelly et al.
patent: 6166572 (2000-12-01), Yamaoka
patent: 6172937 (2001-01-01), Ilkbahar et al.
patent: 6178212 (2001-01-01), Akashi
patent: 6201423 (2001-03-01), Taguchi et al.
patent: 6396888 (2002-05-01), Notani et al.
patent: 6444644 (2002-09-01), Bruckdorfer et al.
patent: 6470405 (2002-10-01), Barth et al.
patent: 6542976 (2003-04-01), Barth et al.
patent: 6570944 (2003-05-01), Best et al.
patent: 6591353 (2003-07-01), Barth et al.
U.S. Appl. No. 2001/0047450 A1, filed Nov. 29, 2001. Gillingham et al. “High Bandwidth Memory Interface”. U.S. Appl. No. 09/182,494 filed Oct. 30, 1998.
JEDEC Solid State Technology Association—JEDEC Standard, “Double Data Rate (DDR) SDRAM Specification”, JESD79. Jun. 2000. 3 cover pages, p. i, and pp. 1-80.
IEEE Journal of Solid-State Circuits, vol. 34, No. 4, “Source-Synchronization and Timing Vernier Techniques for 1.2-GB/s SLDRAM Interface”, by Yasunobu Nakase et al. Apr. 1999. pp. 494-501.
IEEE International Solid-State Circuits Conference, WP 24.3. “A 800MB/s 72 Mb SLDRAM with Digitally-Calibrated DLL”, by Lluis Paris et al. 1999. 10 pages.
ISSCC Slide Supplement—ISSCC 99 / Session 24 / DRAM / Paper WP 24.3. “WP24.3: An 800MB/s 72Mb SLDRAM with Digitally-Calibrated DLL”, by Lluis Paris et al. 1999. pp. 352-353.
Micron Technology Inc.DesignLinearticle entitled, “DDR SDRAM Functionality and Controller Read Data Capture,” vol. 8, Issue 3, 3Q99.
IEEE Micro article entitled, “SLDRAM: High-Performance, Open Standard Memory,” by P. Gillingham et al., Nov./Dec. 1997, pp. 29-39.
Intel Corporation article entitled, “High Speed, High Bandwidth External Cache Bus with a Center-Tapped Termination Scheme,” by Harry Muljono, Naveen Cherukuri

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Apparatus for data recovery in a synchronous chip-to-chip... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for data recovery in a synchronous chip-to-chip..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for data recovery in a synchronous chip-to-chip... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3319225

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.