Apparatus for current ballasting ESD sensitive devices

Details Apparatus for current ballasting ESD sensitive devices Apparatus for current ballasting ESD sensitive devices

2000-05-30

2003-07-01

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C257S361000

Reexamination Certificate

active

06587320

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to current protection of electronic devices and specifically to current ballasting in fully silicided electrostatic discharge sensitive devices.
BACKGROUND OF THE INVENTION
Integrated circuits including metal-oxide-semiconductor (MOS) transistors receive input signals and transfer output signals in the form of a voltage. These devices are typically made with very small device dimensions in order to maximize the amount of circuitry that can be implemented on the integrated circuit and to allow the circuitry to operate at high frequencies yet with minimal power demands. A problem with these devices, however, is their sensitivity to damage from electrical overstresses applied to the input terminals, output terminals or to internal circuit nodes of the integrated circuit. The gate oxides for these devices are typically very thin and can break down if an applied voltage exceeds even relatively low levels. Such breakdown may cause immediate or expedited destruction of transistors or other devices. Excess voltage is often caused by stress in the form of electrostatic discharge (ESD). As is well known, ESD events, although brief, may exhibit relatively large currents, on the order of amperes. In order to combat problems associated with ESD events, manufacturers of MOS devices design protection devices that provide paths through which to discharge nodes rapidly. Protection devices may be positioned between the input buffer or output buffer pads of a device and a source of reference potential (e.g., ground) to quickly conduct the ESD voltage away from the devices that may be harmed. Note that the terms ESD device, ESD protection device, and ESD sensitive device are used interchangeably throughout this document.
FIG. 1
is a top-plan view of one such ESD protection device. The exemplary device is implemented as an N-channel MOS transistor having source and drain regions and a gate electrode over a channel region that separates the source and drain regions. Although the device is implemented as an MOS transistor, it operates, in ESD protection mode as a parasitic bipolar transistor having a collector region corresponding to the drain region, an emitter region corresponding to the source region and a base region corresponding to the channel region. In a typical configuration, the gate electrode is tied to a source of reference potential (e.g. ground) either by a direct connection or through a resistive connection. As is well known, when the potential between the collector and the emitter (V
ce
) of the bipolar transistor becomes greater than a predetermined voltage, known as the snap-back trigger voltage, the voltage V
ce
snaps back to a lower value. The device clamps the voltage at this lower value, known as the snapback holding voltage. In this conduction mode, the transistor presents a very low impedance and, thus, conducts any current to ground.
The ESD protection device shown in
FIG. 1
, includes multiple channels through which the relatively high ESD currents may be conducted in order to reduce the voltage and current stress on the device. Each channel is defined by a metal connecting terminal
4
, in the drain region
2
of the transistor
3
and a corresponding metal connecting terminal
8
in the source region
6
of the transistor. Connecting terminals
4
are connected to solid metal connections
1
. Metal openings or slots
7
are sometimes required for various process reasons. Ideally, during an ESD condition, substantially equal “current paths” are established between each pair of connecting terminals creating multiple nonintersecting and nondiscriminating paths to discharge the ESD current.
Another trend in semiconductor processing is to apply silicide to the source and drain regions of MOS transistors in order to improve their performance. Silicided regions typically exhibit lower surface resistance than the doped silicon that forms the source and drain regions.
Applying silicide to the gate and source regions of an ESD protection device, however, may affect the performance of the device. Because the silicide may have a relatively rough edge next to the gate, this may lead to high local electrical fields and to degradation of the edges by high current densities (and corresponding increases in temperature). Because the silicide has a relatively low sheet resistance the entire device current can collapse into one small device region and cause immediate damage.
Attempts have been made to increase the gate-to-contact spacing in ESD protection devices, placing the silicide farther away from the heat-generating collector-base junction area in attempts to minimize the possibility of silicide failure. One such device is shown in
FIG. 2
, described below. These methods, however, increase the device geometry and require special processing steps for the ESD protection devices to selectively prevent silicide from being applied to portions of the source and drain electrodes of the device.
Attempts also have been made to provide ESD protection, as described in U.S. Pat. No. 5,763,919, by implementing a MOS transistor array structure having dispersed parallel discharge paths. These dispersed parallel discharge paths are formed in the n-well regions and in the N+ drain regions of the structure. The dispersed N+ drain regions are defined by local oxidation or shallow trench isolation (STI). The part of the N+ to substrate junction close to the local oxidation or STI interface may exhibit mechanical stress causing, among other things, electric field focal points, current leakage and susceptibility to breakdown. This structure also has non-linear discharge path resistance due to the N-well, and the performance of the structure is dependent upon the diffusion/well resistance. Another feature of this structure is that the dispersed parallel discharge paths are not isolated from the substrate, thus causing potential breakdown to the substrate (dispersed N+ drain regions) and adding undesirable additional parasitic capacitance (dispersed N+ regions and N-well regions).
SUMMARY OF THE INVENTION
The present invention is embodied in apparatus for current ballasting an ESD protection device. Ballasting resistance is achieved by coupling nonintersecting conductive strips between a common contact pad and a respective plurality of spaced connecting terminals of the ESD protection device. The connecting strips form respective ballasting resistors between the contact pad and the connecting terminals of the ESD device.
According to one aspect of the invention, the conductive strips are formed from metal.
According to another aspect of the invention, the conductive strips are formed from polysilicon.
According to yet another aspect of the invention, the conductive strips are formed from a vertically meandering connection of vias and connecting layers.
According to yet another aspect of the invention, the lateral resistance between the connecting terminals is enhanced by segmenting the drain region of the ESD device locally between each pair of terminals.
According to another aspect of the invention, the lateral resistance between the connecting terminals is enhanced by defining a further gate electrode, having a portion that is parallel to the gate electrode of the ESD device and further portions that extend between the conductive strips.
According to another aspect of the invention, the ESD device is implemented as multiple component parallel-connected ESD devices, each component ESD device having a drain region, a gate region and a source region and including a plurality of nonintersecting conductive strips forming a respective plurality of ballasting resistors between a common electrically conductive terminal and a respective plurality of spaced connecting terminals in the respective drain region of each ESD device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.


REFERENCES:
patent: 4306246 (1981-12-01),

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