Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Electrical signal parameter measurement system
Reexamination Certificate
2011-06-21
2011-06-21
Lau, Tung S (Department: 2857)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Electrical signal parameter measurement system
Reexamination Certificate
active
07966138
ABSTRACT:
The method for creating a test pattern and calculating a fault coverage or the like of the present invention is characterized by creating bridging fault voltage information indicating a voltage of a bridging assumed on the wire derived from an output terminal of a cell, calculating a logical threshold of an input terminal of the cell, extracting bridging fault information on an adjacent wire pair, calculating a detection limit resistance value using the logical threshold, adding the detection limit resistance value to bridging fault voltage information, creating extended bridging fault voltage information, creating a bridging fault list including a bridging fault type based on the extended bridging fault voltage information, creating a test pattern based on the bridging fault list, judging whether or not a bridging fault can be detected through this test pattern, creating fault detection information and calculating a weighted fault coverage based on the fault detection information and bridging fault generation information.
REFERENCES:
patent: 2006/0005094 (2006-01-01), Nozuyama
patent: 2007/0201618 (2007-08-01), Nozuyama
patent: 2007/0260408 (2007-11-01), Nozuyama
patent: 2003-107138 (2003-04-01), None
Nozuyama, et al., A Method for Estimating and Enhancing Test Quality Using Layout Information—A basic method and a few examples (bridge fault Iddq test, weighted stuck-at fault coverage), Technical Report of IEICE (Japan), vol. CPM2002-152, pp. 1-6, Jan. 2003.
C.E. Stroud, et al., Bridging Fault Extraction from Physical Design Data for Manufacturing Test Development, Proc. IEEE International Test Conference, pp. 760-769, Oct. 2000.
V.R. Sar-Dessai, et al., Resistive Bridge Fault Modeling, Simulation and Test Generation, Proc. IEEE International Test Conference, pp. 596-605, 1999.
S. Sengupta, et al., Defect-Based Test: A Key Enabler for Successful Migration to Structural Test, Intel Technology Journal, pp. 1-14, Q1'99.
M. Renovell, et al., The Concept of Resistance Interval: A New Parametric Model for Realistic Resistive bridging Fault, Proc. 13th VLSI Test Symposium, pp. 184-189, 1995.
P. Engelke, et al., Simulating Resistive Bridging and Stuck-At Faults, Proc. International Test Conference, pp. 1051-1059, 2003.
I. Polian, et al., Modeling Feedback Bridging Faults with Non-Zero Resistance, Europian Test Workshop, 4A-3, 2003.
Kabushiki Kaisha Toshiba
Lau Tung S
Turocy & Watson LLP
LandOfFree
Apparatus for creating test pattern and calculating fault... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus for creating test pattern and calculating fault..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for creating test pattern and calculating fault... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2639391