Apparatus for correction of memory errors

Details Apparatus for correction of memory errors Apparatus for correction of memory errors

1979-03-15

1981-02-17

Shaw, Gareth D.

Boots, shoes, and leggings

371 21, 371 38, G06F 1108, G11C 2900

Patent

active

042518636

ABSTRACT:
Apparatus for correcting memory errors by testing the addressable location causing the memory error in realtime. The memory responds to read requests by accessing the contents of the requested addressable location. If the contents of the addressable location contain errors, which are uncorrectable by other means, the memory saves the erroneous data word and the requested addressable location is tested by immediately writing into and reading from the requested addressable location. Two data words are sequentially written into and read from the requested addressable location which cause both a one and a zero to be written into each bit position of the requested addressable location. If the reads reveal an error at any bit positions of the requested addressable location, the corresponding bit positions of the erroneous data word are complimented and the resultant is transferred to the requestor using the normal data path. A hold signal is generated to halt the requestor during the time required to test the requested addressable location and correct the erroneous data word.

REFERENCES:
patent: 3999051 (1976-12-01), Petschauer
patent: 4031374 (1977-06-01), Groudan et al.
patent: 4037091 (1977-07-01), Beuscher
patent: 4139148 (1979-02-01), Scheuneman et al.
patent: 4163147 (1979-07-01), Scheuneman et al.
patent: 4175692 (1979-11-01), Watanabe
Black, C. J. et al., "Development of a Space Borne Memory with a Single Error an Erasure Correction Scheme", 7th Ann. Int. Conf. on Fault Tolerant Computing by IEEE Comp. Soc., 1977, pp. 50-55.

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