Television – Image signal processing circuitry specific to television – Transition or edge sharpeners
Reexamination Certificate
1999-04-22
2002-07-23
Miller, John (Department: 2714)
Television
Image signal processing circuitry specific to television
Transition or edge sharpeners
C348S606000, C348S607000, C348S625000
Reexamination Certificate
active
06424383
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a vertical contour correcting device for a video signal utilized in a television receiver etc.
BACKGROUND ART
Referring to
FIGS. 19
,
20
,
21
,
22
and
23
, an example of a conventional vertical contour correcting circuit will now be described. As shown in
FIG. 19
, the conventional vertical contour correcting device VCC has an input port
1
, a vertical contour component extracting device
3
, an adder
7
, a non-linear processor
18
, and an output port
2
. The input port
1
receives input of a digital video signal S
1
from an external video signal source (not shown). The vertical contour component extracting device
3
is connected to the input port
1
and extracts vertical contour components of the input digital video signal S
1
to generate a vertical contour component signal S
1
v, and it also delays the present video signal S
1
to be corrected for one line to generate a primary delayed digital video signal S
1
′.
FIG. 20
shows the structure of the vertical contour component extracting device
3
in detail. The vertical contour component extracting portion
3
includes a first one-line delay unit
19
, a second one-line delay unit
20
, a first coefficient unit
21
, a second coefficient unit
22
, a third coefficient unit
23
, and an adder
24
. The first one-line delay unit
19
and the first coefficient unit
21
are connected to the input port
1
to receive the input of the digital video signal S
1
together. The first one-line delay unit
19
delays the digital video signal S
1
by one line to generate the primary delayed digital video signal S
1
′. The first coefficient unit
21
multiplies the digital video signal S
1
by a first coefficient K1 to attenuate the present digital video signal S
1
and generates a first digital video sub-signal S
1
S. While the first coefficient K1 can take an arbitrary value, K1=−¼ in this example.
The second one-line delay unit
20
and the second coefficient unit
22
are connected to the first one-line delay unit
19
to receive input of the primary delayed digital video signal S
1
′. The one-line delay unit
20
further delays the input primary delayed digital video signal S
1
′ by one line to generate a secondary delayed digital video signal S
1
″. The second coefficient unit
22
multiplies the input primary delayed digital video signal S
1
′ by a second coefficient K2 to attenuate the primary delayed digital video signal S
1
′ and generates a second digital video sub-signal S
1
′S. As stated above, the adder
7
(
FIG. 19
) is connected to the first one-line delay unit
19
to obtain the input of the primary delayed digital video signal S
1
′.
The third coefficient unit
23
is connected to the one-line delay unit
20
to receive input of the digital video signal S
1
″. The coefficient unit
23
multiplies the digital video signal S
1
″by a third coefficient K3 to attenuate the digital video signal S
1
″ and generates a third digital video sub-signal S
1
″S. The above-mentioned three coefficients K1, K2 and K3 can take such arbitrary values smaller than one, such that the sum of the three coefficients is equal to zero. In this example, the values are set as K1=−{fraction (1/4,)} K2={fraction (1/2,)} and K3=−{fraction (1/4.)} The vertical contour component extracting device
3
can be a vertical filter structure providing a desired frequency characteristic.
The adder
24
is connected to the first coefficient unit
21
, second coefficient unit
22
, and coefficient unit
23
to receive input of the first digital video sub-signal S
1
S, second digital video sub-signal S
1
′S, and third digital video sub-signal S
1
″S. The adder
24
adds the three input digital video sub-signals S
1
S, S
1
′S, and S
1
″S which are respectively delayed for one line to generate and output the vertical contour component signal S
1
v to the non-linear processor
18
(FIG.
19
).
FIG. 21
shows the structure of the non-linear processor
18
. The non-linear processor
18
includes a coring circuit
25
, a horizontal low-pass filter
26
, a sequential coefficient unit
27
, and a limiter
28
. The coring circuit
25
is connected to the adder
24
in the vertical contour component extracting device
3
to receive input of the vertical contour component signal S
1
v. The coring circuit
25
then applies noise-removal to the vertical contour component of the input vertical contour component signal S
1
v to generate a first vertical contour component signal.
The horizontal low-pass filter
26
is connected to the coring circuit
25
to receive input of the first vertical contour component signal. The horizontal low-pass filter
26
then removes high-frequency component of the input vertical contour component signal to generate a second vertical contour component signal.
The sequential coefficient unit
27
is connected to the horizontal low-pass filter
26
to receive input of the second vertical contour component signal. The sequential coefficient unit
27
multiplies the input second vertical contour signal by a given coefficient to generate a first vertical contour correction signal.
The limiter
28
is connected to the sequential coefficient unit
27
to receive input of the first vertical contour correction signal. The limiter
28
then applies given band limitation to the first vertical contour correction signal to generate a second vertical contour correction signal S
1
vc.
Referring back to
FIG. 19
again, as stated above, the non-linear processor
18
applies non-linear processing to the vertical contour component signal S
1
v outputted from the vertical contour component extracting device
3
to generate the vertical contour correction signal S
1
vc.
The adder
7
is connected to the first one-line delay unit
19
in the vertical contour component extracting device
3
and the non-linear processor
18
to receive input of the primary delayed digital video signal S
1
′ to be corrected and the second vertical contour correction signal S
1
vc. The adder
7
then adds the input vertical contour correction signal S
1
vc and primary delayed digital video signal S
1
′ to reproduce a vertical contour corrected video signal S
1
C with corrected vertical contour. The vertical contour corrected video signal S
1
C is externally outputted through the output port
2
.
FIG. 2
shows an image represented by the digital video signal S
1
. In
FIG. 2
, the ordinate shows the vertical scanning direction Dv of the image, and the abscissa shows the horizontal scanning line direction Dh. In this image, ∘ indicates a pixel representing the image.
FIG. 2
shows an example in which the digital video signal S
1
is represented by pixels PA, PB and PC at three different levels.
That is to say, they are first-level pixels PA indicated by ∘ containing A, second-level pixels PB indicated by ∘ containing B, and third-level pixels PC indicated by ∘ containing C.
All pixels on the horizontal line L
0
and line L
1
and the pixels on the horizontal line L
2
except the pixel on the vertical line &agr; are the first-level pixels PA. The pixel on the vertical line &agr; on the horizontal line L
2
is the second-level pixel PB. All pixels on the horizontal lines L
3
and L
4
are the third-level pixels PC. When the levels of the pixels PA, PB, and PC are represented as Lpa, Lpb, and Lpc, they are in the relation Lpa>Lpc>Lpb. That is to say, in this case, the pixel PB on the vertical line &agr; and the horizontal line L
2
is an impulse noise. The presence of such impulse noise is likely to cause the viewers to feel as if the S/N ratio of the image is deteriorated.
FIG. 22
shows signal levels of the digital video signal S
1
and the vertical contour corrected video signal S
1
C in the horizontal positions &agr;−1 and &agr;+1. For the vertical contour corrected video signal S
1
C, ∘ with P and ∘
Nio Yutaka
Okumura Naoji
Tanaka Kazuhito
Terai Katsumi
Matsushita Electric - Industrial Co., Ltd.
Miller John
Wenderoth , Lind & Ponack, L.L.P.
Yenke Brian
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