Apparatus for correcting multiple errors in data words read from

Details Apparatus for correcting multiple errors in data words read from Apparatus for correcting multiple errors in data words read from

1979-01-15

1980-11-25

Atkinson, Charles E.

Excavating

G06F 1110, G11C 2900

Patent

active

042362474

ABSTRACT:
An apparatus for a semiconductor memory in a data processing system, which performs real-time single and double error detection and correction, as well as triple error detection. The syndrome of the data word read from the memory is stored when a first error is detected. Said stored syndrome is used later for error correction when a second error is detected and in parallel it is combined logically with the actual syndrome word for deriving the syndrome corresponding to the second error, said second syndrome serving for error correction. The second syndrome can also be stored for permitting real-time triple error detection.

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patent: 4072853 (1978-02-01), Barlow et al.
patent: 4077028 (1978-02-01), Lui et al.
patent: 4117458 (1978-09-01), Burghard et al.
patent: 4168486 (1979-09-01), Legory
Hsiao, A Class of Optimal Minimum Odd-Weight-Column SEC-DED Codes, IBM J. Res. Develop., Jul. 1970, 395-401.

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