Boots – shoes – and leggings
Patent
1987-11-25
1990-07-31
Harkcom, Gary V.
Boots, shoes, and leggings
36472801, 364900, 3649207, 358464, 382 42, 382 54, G06F 1568, G06F 938
Patent
active
049454960
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
This invention relates to a picture processing apparatus. More particularly, this invention is directed to a picture processing apparatus for performing convolution processing on plural items of pixel data stored in a frame memory, on a time-sharing basis using a predetermined coefficient matrix comprising rows and colums.
For such purposes as sharpening a picture, removing background noise from a picture, etc., conventional practice is to perform convolution processing on pixel data in a frame memory using a predetermined weighted coefficient matrix comprising rows and columns.
FIG. 4(a) illustrates a coefficient matrix of five rows and five columns, and FIG. 4(b) illustrates 256.times.256 items of pixel data A.sub.11, A.sub.12, . . . , A.sub.256256 in a frame memory. Weighted coefficients C.sub.11, C.sub.12, . . . , C.sub.55 in the coefficient matrix have weighted values for attaining the aforementioned purposes.
In order to perform convolutioon processing with regard to the pixel data in a frame memory of the kind shown in FIG. 4(b) with a coefficient matrix of the kind shown in FIG. 4(a), a convolution processor is used. With a conventional processor, partial convolution processing is performed with regard to one predetermined row of pixel data in the frame memory. The results of this intermediatre processing are stored in a buffer RAM. Next, the intermediate results just stored in the buffer RAM are read out, and added to the results of the next partial convolution processing obtained from the convolution processor. The resulting sum is repeatedly stored at the address in the buffer RAM where the preceding intermediate processing results were stored, and the sum is read out from this address. Thus, convolution processing is performed on a time-sharing basis.
With the 5.times.5 coefficient matrix of the kind shown in FIG. 4(a), for example, this time-sharing convolution processing is executed by being split into five stages. When the convolution processing is performed with respect to the third row of pixel data in FIG. 4(b), partial convolution processing is carried out between the first row of the coefficient matrix and the first through 256 columns of pixel data in the first row in the first stage of processing. As shown in FIG. 6, ##EQU1## is stored in third through 254th columns of the first row of the buffer RAM as the respective intermediate processing results of the convolution processing. At this time, invalid data (indicated by the symbol "*" in the drawings) enter the first, second, 255th and 256th columns. Next, in the second stage of processing, the intermediate processing results stored in the buffer RAM are read out and, at the same time, the convolution processor performs partial convolution processing between the second row of the coefficient matrix and the first through 256th columns of pixel data in the second row. These partial results and the preceding intermediate processing results stored in a data latch circuit are added and the new intermediate processing results obtained from the addition are stored by rewriting the preceding intermediate processing results in the third through 254th columns of the buffer RAM, as shown in FIG. 6(b), at a write timing controlled by a bus buffer. Thus, ##EQU2## are written in the third through 254th columns of the buffer RAM.
The third, fourth and fifth stages of processing are executed through this procedure to store intermediate processing results of the kind shown in FIGS. 6(c), (d) and (e) in the first row of the buffer RAM. When the fifth stage of processing is performed, 5.times.5 matrix convolution processing with respect to the third row of the frame memory will be completed, so that results of the kind shown in FIG. 6(e) can be obtained. In other words, ##EQU3##
However, when the high-speed processing is attempted with this convolution apparatus for performing convolution processing on a time-sharing basis, a prescribed period of time is required for reading the intermediate processing results from the buffe
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patent: 4635292 (1987-01-01), Mori et al.
patent: 4785409 (1988-11-01), Badono et al.
Kurakake Mitsuo
Muraoka Yutaka
Otsuka Shoichi
Bayerl Raymond J.
Fanuc Ltd
Harkcom Gary V.
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