Television – Format conversion – Involving both line number and field rate conversion
Patent
1992-06-09
1994-05-03
Groody, James J.
Television
Format conversion
Involving both line number and field rate conversion
348454, H04N 1120
Patent
active
053092244
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to an apparatus for converting the color television system among the NTSC system, PAL system, and the like.
BACKGROUND ART
The conversion of color television system (will be termed simply "television system" hereinafter) involves two major items of conversion as follows.
(1) Conversion of the number of lines and the number of fields.
(2) Conversion of the carrier frequency and modulation mode for the color signal.
Among these items, the number of lines and the number of fields are generally converted via a digital signal processing operation using a digital memory or the like, and the color signal is conventionally converted through decoding and encoding via an analog signal processing operation in general.
A conventional apparatus for converting the television system based on the above-mentioned scheme will be explained with reference to FIG. 5.
FIG. 5 is a block diagram of the conventional television system conversion apparatus. In the figure, symbol 1 denotes an input terminal for receiving a television signal to be converted. 2 is a luminance/chrominance signal separation circuit which separates the input television signal into a luminance signal and a chrominance signal. 38 is a chrominance signal decoding circuit (decoder) performing analog signal processing, and it decodes the chrominance signal into two color difference signals U and V. 39 is an analog-to-digital converter (A/D converter) for the colo signal, and it converts the two color difference signals into a digital signal by multiplexing. 40 is a digital memory for the color signal, and it is used to convert the number of lines and the number of fields through the extraction or interpolation process for the digital color difference signals in response to the controlled write clock and read clock. 41 and 42 are digital-to-analog converters (D/A converters) for the color signal, and they convert the two color difference signals, which have been subjected to the line conversion and field conversion, into analog signals. 43 is a chrominance signal encoding circuit (encoder) performing analog signal processing, and it encodes the two analog color difference signals into a chrominance signal. 6, 9 and 12 are respectively an A/D converter, a digital memory and a D/A converter for the luminance signal, and their operations are identical to those elements processing the color signal. 14 is a sync separation circuit which separates the sync signal from the luminance signal. 44 is a write clock generation circuit and 45 is a read clock generation circuit, with both clocks being controlled for the implementation of line conversion and field conversion. 13 is an output buffer circuit which delivers the converted luminance signal and chrominance signal to an output terminal 19.
The operation of the conventional television system conversion apparatus arranged as described above will be explained by taking an example of the case where a television signal of NTSC system received on the input terminal 1 is converted into a television signal of PAL system on the output terminal 19. The chrominance signal of NTSC system separated by the luminance/chrominance signal separation circuit 2 is demodulated with a right-angle 2-phase carrier of 3.58 MHz by the NTSC-based chrominance signal decoder 38 so that it is decoded into two color difference signals U and V of NTSC system. The decoded color difference signals of NTSC system are converted into digital signals by the A/D converter 39, and thereafter stored in the digital memory 40 in response to the write clock provided by the write clock generation circuit 44. Since the write clock is locked to the sync signal of NTSC system provided by the sync separation circuit 14, the two color difference signals of NTSC system are stored in the digital memory 40 such that their line number and field number are coincident with the line address and field address in the address space of the digital memory 40. Namely, 525 line numbers and 60 field numbers correspond to the addresses. Th
REFERENCES:
patent: 4567507 (1986-01-01), Kusakabe
patent: 4568963 (1986-02-01), Sakai et al.
patent: 4751573 (1988-06-01), Kubota
patent: 5194937 (1993-04-01), Lee et al.
patent: 5218429 (1993-06-01), Katagiri
Kawabe Toshiyuki
Usuki Naoshi
Grant Chris
Groody James J.
Matsushita Electric - Industrial Co., Ltd.
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