Apparatus for converting a digital value into an analog signal

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

Reexamination Certificate

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Details

C341S145000

Reexamination Certificate

active

06812877

ABSTRACT:

BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to an apparatus for converting a digital value including “a” bits into an analog signal.
Such an apparatus generally includes a voltage divider chain in which each value that can be assumed by the digital value to be converted has an associated tap connected to the output connection of the apparatus via a selection switch.
Such an apparatus is shown by way of example in FIG.
1
A. The apparatus shown is designed for converting a digital value including three bits into an analog signal.
The voltage divider chain: includes seven resistors R connected in series; has reference voltages REF-HI and REF-LO applied to the ends; and has taps A
0
to A
7
.
The taps A
0
to A
7
are the starting points for lines L
0
to L
7
, which are connected to an output connection OUT of the apparatus via selection switches S
0
to S
7
.
The selection switches S
0
to S
7
are controlled by a decoder DEC on the basis of the digital value that will be converted. The decoder DEC has an input connection IN which is used to input the digital value that will be converted into an analog signal.
By way of example, the decoder DEC operates such that:
it closes the selection switch S
0
and keeps all the other selection switches open when the digital value to be converted is 000;
it closes the selection switch S
1
and keeps all the other selection switches open when the digital value to be converted is 001;
it closes the selection switch S
2
and keeps all the other selection switches open when the digital value to be converted is 010;
it closes the selection switch S
3
and keeps all the other selection switches open when the digital value to be converted is 011;
it closes the selection switch S
4
and keeps all the other selection switches open when the digital value to be converted is 100;
it closes the selection switch S
5
and keeps all the other selection switches open when the digital value to be converted is 101;
it closes the selection switch S
6
and keeps all the other selection switches open when the digital value to be converted is 110; and
it closes the selection switch S
7
and keeps all the other selection switches open when the digital value to be converted is 111.
As a result, the output connection OUT of the arrangement provides an analog voltage corresponding to the digital value.
FIG. 1B
shows a symbol used later for the apparatus shown in FIG.
1
A.
An apparatus of the type shown in
FIG. 1A
can also be in a form such that it converts the digital value into two analog signals that can be used as differential signals.
Such an apparatus is shown in FIG.
2
A. The apparatus shown in
FIG. 2A
contains, like the apparatus shown in
FIG. 1A
, a voltage divider chain which: includes seven resistors R connected in series, has reference voltages REF-HI and REF-LO applied to the ends, and has taps A
0
to A
7
.
The taps A
0
to A
7
are again the starting points for lines L
0
to L
7
, which are connected to an output connection OUT
1
of the apparatus via selection switches S
0
to S
7
.
The taps A
0
to A
7
are also the starting points for lines L
10
to L
17
, which are connected to a second output connection OUT
2
of the apparatus via selection switches S
10
to S
17
.
The selection switches S
0
to S
7
and S
10
to S
17
are controlled by a decoder DEC on the basis of the digital value that will be converted; the decoder DEC has an input connection IN which is used to input the digital value that will be converted into an analog signal.
In more precise terms, respectively one of the selection switches S
0
to S
7
and at the same time one of the selection switches S
10
to S
17
are closed, while all the other selection switches are respectively open.
As a result, the apparatus shown in
FIG. 2A
outputs two respective analog voltages. If the selection switches S
0
to S
7
and S
10
to S
17
are actuated such that the analog signal corresponding to the digital value which is to be converted is formed by subtracting the signal which is output from the output signal OUT
2
from the signal which is output from the output connection OUT
1
(or vice versa), this allows interference to be eliminated.
By way of example, the decoder DEC operates such that:
it closes the selection switches S
0
and S
10
and keeps all the other selection switches open when the digital value to be converted is 000;
that it closes the selection switches S
2
and S
11
and keeps all the other selection switches open when the digital value to be converted is 001;
that it closes the selection switches S
4
and S
12
and keeps all the other selection switches open when the digital value to be converted is 010;
that it closes the selection switches S
6
and S
13
and keeps all the other selection switches open when the digital value to be converted is 011;
that it closes the selection switches S
7
and S
13
and keeps all the other selection switches open when the digital value to be converted is 100;
that it closes the selection switches S
7
and S
12
and keeps all the other selection switches open when the digital value to be converted is 101;
that it closes the selection switches S
7
and S
11
and keeps all the other selection switches open when the digital value to be converted is 110; and
that it closes the selection switches S
7
and S
10
and keeps all the other selection switches open when the digital value to be converted is 111.
FIG. 2B
shows a symbol used later for the apparatus shown in FIG.
2
A.
If an apparatus as shown in
FIG. 1A
or as shown in
FIG. 2A
is part of an integrated circuit, the voltage divider chain is generally in the form of a long resistive track, i.e. without discrete resistive components. In this case, the resistive track and the taps are in a form and are arranged such that the resistive track between two adjacent taps has a respective electrical resistance which corresponds to the electrical resistance of one of the resistors R in the arrangements shown in
FIGS. 1A and 2A
.
An apparatus having a voltage divider chain implemented in this manner is shown in FIG.
3
. The apparatus shown in
FIG. 3
corresponds to the apparatus shown in FIG.
2
A. Identical references denote components which are the same or which correspond to one another. The only difference between the apparatus shown in FIG.
3
and the apparatus shown in
FIG. 2A
is that the apparatus shown in
FIG. 3
has no discrete resistors R. Instead, a resistive track RB is provided which, between adjacent taps, has a respective electrical resistance which corresponds to the electrical resistance of one of the resistors R in the arrangements shown in
FIGS. 1A and 2A
.
By omitting the lines S
10
to S
17
, the selection switches S
10
to S
17
and the second output connection OUT
2
, an apparatus is obtained which corresponds to the apparatus shown in FIG.
1
A.
For the sake of completeness, it will be noted that the resistive track RB is formed by a polylayer on the semiconductor chip containing the integrated circuit. Of the lines L
0
to L
7
and L
10
to L
17
coming from the taps A
0
to A
7
, the first portion is likewise formed by a polylayer and the second portion is formed by a metal layer provided above the polylayer. The crossover for the lines from the polylayer into the metal layer, more precisely the plated-through hole provided for this purpose, is provided in order to connect these layers at a great distance from the taps A
0
to A
7
so that the plated-through hole cannot have any effect on the current flowing through the resistive track. In addition, it will be noted that no or just a very small current can flow through the lines L
0
to L
7
and L
10
to L
17
, because this would affect the D/A conversion. This incidentally also applies to all other apparatus in which D/A conversion is carried out using voltage divider chains.
Implementing the voltage divider chain using a resistive track is relatively easy, but under some circumstances it gives rise to problems when integrating a D/A converter containing such a resis

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