Boots – shoes – and leggings
Patent
1983-04-20
1985-05-28
Shaw, Gareth D.
Boots, shoes, and leggings
G06F 1100
Patent
active
045204586
ABSTRACT:
An apparatus for controlling the writing of data from a processor into a memory having different read and write times, wherein the memory is connected directly to the processor through address and data buses without the use of an input/output port. A timer circuit is connected to the buses and memory and is controlled by the processor to produce a write timing signal which controls the writing of data into the memory. The processor is placed in a holding state, based on the write timing signal, for a period long enough to assure that the data will be written into the memory in its entirety.
REFERENCES:
patent: 4092728 (1978-05-01), Baltzer
patent: 4388695 (1983-06-01), Heinemann
Hattori Seiichi
Kanda Kunio
Fanuc Ltd
Lee Jameson
Shaw Gareth D.
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