Chemistry: electrical and wave energy – Apparatus – Electrolytic
Reexamination Certificate
2001-05-15
2004-10-12
Nguyen, Nam (Department: 1753)
Chemistry: electrical and wave energy
Apparatus
Electrolytic
C204S230200, C204S242000, C204S284000, C204S297050, C204SDIG007
Reexamination Certificate
active
06802946
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to electrodeposition process technology and, more particularly, to an electrodeposition process and apparatus that yield planar deposition layers.
2. Description of Related Art
A conventional semiconductor device generally includes a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers, such as silicon dioxide interlayers, and conductive paths or interconnects made of conductive materials. The interconnects are usually formed by filling a conductive material in trenches etched into the dielectric interlayers. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. The interconnects formed in different layers can be electrically connected using vias or contacts. A conductive material filling process of filling such features, i.e. via openings, trenches, pads or contacts, can be carried out by depositing a conductive material over the substrate including such features. Excess conductive material on the substrate can then be removed using a planarization and polishing technique such as chemical mechanical polishing (CMP).
Copper (Cu) and Cu alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The preferred method of Cu deposition is electrodeposition. During fabrication, copper is electroplated or electrodeposited on substrates that are previously coated with barrier and seed layers. Typical barrier materials generally include tungsten (W), tantalum (Ta), titanium (Ti), their alloys and their nitrides. A typical seed layer material for copper is usually a thin layer of copper that is CVD or PVD deposited on the aforementioned barrier layer.
There are many different Cu plating system designs. For example, U.S. Pat. No. 5,516,412, issued on May 14, 1996 to Andricacos et al., discloses a vertical paddle plating cell that is configured to electrodeposit a film on a flat article. U.S. Pat. No. 5,985,123, issued on Nov. 16, 1999 to Koon, discloses yet another vertical electroplating apparatus which purports to overcome the non-uniform deposition problems associated with varying substrate sizes.
During the Cu electrodeposition process, specially formulated plating solutions or electrolytes are used. These solutions or electrolytes contain ionic species of Cu and additives to control the texture, morphology, and plating behavior of the deposited material. Additives are needed to make the deposited layers smooth and somewhat shiny.
FIGS. 1 through 2
exemplify a conventional electrodeposition method and apparatus.
FIG. 1A
illustrates a substrate
10
having an insulator layer
12
formed thereon. Using conventional etching techniques, features such as a row of small vias
14
and a wide trench
16
are formed on the insulator layer
12
and on the exposed regions of the substrate
10
. Typically, the widths of the vias
14
are sub-micronic. The trench
16
shown in this example, on the other hand, is wide and has a small aspect ratio. The width of the trench
16
may be five to fifty times or more greater than its depth.
FIGS. 1B-1C
illustrate a conventional method for filling the features with copper material.
FIG. 1B
illustrates that a barrier/glue or adhesion layer
18
and a seed layer
20
are sequentially deposited on the substrate
10
and the insulator
12
. After depositing the seed layer
20
, as shown in
FIG. 1C
, a conductive material layer
22
(e.g., a copper layer) is partially electrodeposited thereon from a suitable plating bath or bath formulation. During this step, an electrical contact is made to the copper seed layer
20
and/or the barrier layer
18
so that a cathodic (negative) voltage can be applied thereto with respect to an anode (not shown). Thereafter, the copper material layer
22
is electrodeposited over the substrate surface using plating solutions, as discussed above. By adjusting the amounts of the additives, such as chloride ions, a suppressor/inhibitor, and an accelerator, it is possible to obtain bottom-up copper film growth in the small features.
As shown in
FIG. 1C
, the copper material
22
completely fills the vias
14
and is generally conformal in the large trenches
16
, because the additives that are used are not operative in large features. Here, the Cu thickness t
1
at the bottom surface of the trench
16
is about the same as the Cu thickness t
2
over the insulator layer
12
. As can be expected, to completely fill the trench
16
with the Cu material, further plating is required.
FIG. 1D
illustrates the resulting structure after additional Cu plating. In this case, the Cu thickness t
3
over the insulator layer
12
is relatively large and there is a step height s
1
from the top of the Cu layer on the insulator layer
12
to the top of the Cu layer
22
in the trench
16
. For IC applications, the Cu layer
22
needs to be subjected to CMP or other material removal processes so that the Cu layer
22
as well as the barrier layer
18
on the insulator layer
12
are removed, thereby leaving the Cu layer only within the features
14
and
16
. These removal processes are known to be quite costly.
Methods and apparatus to achieve a generally planar Cu deposit as illustrated in
FIG. 1E
would be invaluable in terms of process efficiency and cost. The Cu thickness t
5
over the insulator layer
12
in this example is smaller than the traditional case as shown in
FIG. 1D
, and the step height s
2
is also much smaller than the step height s
1
. Removal of the thinner Cu layer in
FIG. 1E
by CMP or other methods would be easier, providing important cost savings.
In U.S. Pat. No. 6,176,992 B1 entitled “Method and Apparatus for Electrochemical Mechanical Deposition”, commonly owned by the assignee of the present invention, an electrochemical mechanical deposition (ECMD) technique is disclosed that achieves deposition of the conductive material into cavities on a substrate surface while minimizing deposition on the field regions by polishing the field regions with a pad as the conductive material is deposited, thus yielding planar copper deposits. The plating electrolyte in this application is supplied to the small gap between the pad and the substrate surface through a porous pad or through asperities in the pad.
U.S. patent application Ser. No. 09/511,278, entitled “Pad Designs and Structures for a Versatile Materials Processing Apparatus” filed Feb. 23, 2000, now U.S. Pat. No. 6,413,388 B1, which is commonly owned by the assignee of the present invention, describes various shapes and forms of holes in pads through which electrolyte flows to a wafer surface.
Another invention described in U.S. patent application Ser. No. 09/740,701, entitled “Plating Method and Apparatus That Creates a Differential Between Additive Disposed on a Surface and a Cavity Surface of a Work Piece Using an External Influence”, filed Dec. 18, 2000, provides a method and apparatus for “mask-pulse plating” a conductive material onto a substrate by intermittently moving the mask, which is placed between the substrate and the anode, into contact with the substrate surface and applying power between the anode and the substrate during the process. Yet another invention described in U.S. patent application Ser. No. 09/735,546, entitled “Method of and Apparatus for Making Electrical Contact to Wafer Surface For Full-Face Electroplating or Electropolishing”, filed Dec. 14, 2000, now U.S. Pat. No. 6,482,307, provides complete or full-face electroplating or electropolishing of the entire wafer frontal side surface without excluding any edge area for the electrical contacts. This method uses an anode having an anode area, and electrical contacts placed outside the anode area. During the process, the wafer is moved with respect to the anode and the electrical contacts such that a full-face deposition over the entire wafer frontal surface is achi
Basol Bulent M.
Lindquist Paul
Mutschler Brian L.
Nguyen Nam
NuTool Inc.
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