Apparatus for controlling the access of processors at a data lin

Details Apparatus for controlling the access of processors at a data lin Apparatus for controlling the access of processors at a data lin

1981-10-13

1984-02-28

Shaw, Gareth D.

Boots, shoes, and leggings

G06F 1500

Patent

active

044344660

ABSTRACT:
An apparatus for controlling the access of a plurality of microprocessors at a data line. The microprocessors are connected by interface components or blocks, logic switching circuits and bus drivers with two lines or conductors. An access request or demand of a processor initiates a signal change at the first line. This signal change causes the transformation of data which is specific to the processor into a delay or a priority signal, upon the occurrence of which there is accomplished a signal change of the second line. As a function thereof there appears at an input of the interface component a signal change which is indicative of the availability of the data line. Upon simultaneous occurrence of access requests or demands of a number of processors the signal change of the second line is brought about by that processor whose priority signal possesses the smallest delay. The signal change of the second line prevents the occurrence of the priority signals possessing the greater time-delays and which are correlated to the remaining processors. At these processors there thus cannot occur any signal change at the input of the related interface component or block and which indicates the availability of the data line.

REFERENCES:
patent: 3699529 (1972-10-01), Beyers et al.
patent: 4038644 (1977-07-01), Duke et al.
patent: 4137565 (1979-01-01), Mager et al.
patent: 4223380 (1980-09-01), Antonaccio et al.

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