Apparatus for controlling outputs of read data in a semiconducto

Details Apparatus for controlling outputs of read data in a semiconducto Apparatus for controlling outputs of read data in a semiconducto

1990-11-09

1992-10-27

Bowler, Alyssa H.

Static information storage and retrieval

Addressing

Sync/clocking

365233, 36518901, 36518905, 36518908, G11C 700, G11C 800

Patent

active

051595737

ABSTRACT:
An apparatus for controlling outputs of read data in a semiconductor memory device, includes a plurality of output circuits, through which read data are supplied to an external circuit, an output controlling circuit which controls output operation of the output circuits, an address change detecting circuit which supplies an address detecting signal to the output controlling circuit, and a timing controlling circuit which controls the timing by which an output controlling signal of the output controlling circuit is supplied to the output circuits. The timing controlling circuit controls the timing of discharge in the output terminals of the output circuits, so that the discharge occurs in the output circuits sequentially with a predetermined time interval. Consequently, noise which affects the output circuits' ability to receive read data is prevented during discharge.

REFERENCES:
patent: 4672587 (1987-06-01), Geiger et al.
patent: 4858188 (1989-08-01), Kobayashi
patent: 4891793 (1990-01-01), Anami
patent: 4894803 (1990-01-01), Aizaki
patent: 4903240 (1990-02-01), Von Flue
patent: 4908796 (1990-03-01), Lee et al.
patent: 4928265 (1990-05-01), Higuchi et al.
patent: 4972374 (1990-11-01), Wang et al.
patent: 5025422 (1991-06-01), Moriwaki et al.

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