Apparatus for controlling I/O interrupt in multiprocessor system

Details Apparatus for controlling I/O interrupt in multiprocessor system Apparatus for controlling I/O interrupt in multiprocessor system

1984-06-21

1987-02-17

Chan, Eddie P.

Boots, shoes, and leggings

G06F 946, G06F 1516

Patent

active

046444653

ABSTRACT:
An apparatus for controlling interrupts is provided in a system controller SC of a multiprocessor system in which a plurality of instruction processors IP share a main storage MS and a channel controller CHC through the system controller SC. The apparatus for controlling interrupts holds I/O interrupt control data for each of the instruction processors IP, and selects the most suitable instruction processor IP to process an I/O interrupt, without receiving responses from all of the instruction processors IP.

REFERENCES:
patent: 4271468 (1981-06-01), Christensen et al.
patent: 4386400 (1983-05-01), Cope et al.
patent: 4476524 (1984-10-01), Brown et al.

Affiliated with

Also associated with

Rating

Apparatus for controlling I/O interrupt in multiprocessor system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Apparatus for controlling I/O interrupt in multiprocessor system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus for controlling I/O interrupt in multiprocessor system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1940245