Apparatus for controlling FIFO buffer data transfer by monitorin

Details Apparatus for controlling FIFO buffer data transfer by monitorin Apparatus for controlling FIFO buffer data transfer by monitorin

1995-01-04

1998-06-23

Lall, Parshotam S.

39520061, 39520062, 39520064, 39520065, 395872, 395876, 395877, 395880, G06F 1300, G06F 1314

Patent

active

057713561

ABSTRACT:
This invention provides efficient and flexible data transfer management for a First-In First-Out (FIFO) buffer connects to a system bus and implements multiple data thresholds (e.g., two). Data transfer by the FIFO is controlled by either casually or more aggressively acquiring the system bus based on the amount of data inside the FIFO and on the state of the system bus. By balancing the bus activity level against the FIFO data level, bus access is facilitated at times when the bus has lower activity. This makes the FIFO less obtrusive when moving data across the bus. As a result, the bus is used more efficiently. The system bus is casually acquired when the FIFO data level reaches a soft threshold and the system bus is idle. Casual control of the system bus is relinquished when request from another device sharing the bus is received and a predetermined amount of data has been transferred. On the other hand, the system bus is more aggressively acquired when the FIFO data level reaches a hard threshold. Aggressive control of the system bus is relinquished only when data transfer is complete or when there is an emergency condition such as bus error. The thresholds can be dynamically adjusted based on the bus activity level. In another embodiment of the present invention, the amount of data transfer varies depending on whether the soft or hard threshold is crossed.

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