Multiplex communications – Wide area network – Packet switching
Patent
1994-01-31
1995-01-10
Marcelo, Melvin
Multiplex communications
Wide area network
Packet switching
370 79, 370 84, 370 941, H04J 316, H04L 1266
Patent
active
053814118
ABSTRACT:
A bit rate control circuit of the present invention includes a timer controller and a memory. In one aspect of the present invention, words stored in the memory are addressed by addresses corresponding to data channels. Each of the words includes an enable flag, a set value and an operation value. The set values are determined based on bit rates assigned to the corresponding data channels. The words are scanned at constant intervals. The operation values are updated by adding one when the enable flag is active, in each scan, and if the updated operation value reaches the set value, a command to generate an ATM cell for the corresponding data channel is issued.
REFERENCES:
patent: 4763319 (1988-08-01), Rozenblit
patent: 5117417 (1992-05-01), Danner
patent: 5128924 (1992-07-01), Le Bihan
patent: 5189672 (1993-02-01), Le Bihan
Ohno Koichi
Tachibana Tetsuo
Fujitsu Limited
Marcelo Melvin
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