Patent
1993-12-20
1995-06-20
Nguyen, Phu K.
G06F 1310
Patent
active
054267340
ABSTRACT:
An apparatus for controlling an image display device such as the CRT includes a dual port memory having a first memory and a second memory. Data may be written into a first memory and read from the first memory at any time. Data is sequentially read from the second memory to provide information for the display. Data is manipulated during a data transfer cycle, a dynamic memory refresh cycle, a memory write cycle and a memory read cycle. Data is transmitted between the first memory and second memory during a data transfer cycle. A cycle reconciliation circuit prioritizes the manner in which the cycles occur giving top priority to the data transfer cycle.
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Nguyen Phu K.
Seiko Epson Corporation
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