Apparatus for conditioning priority arbitration

Details Apparatus for conditioning priority arbitration Apparatus for conditioning priority arbitration

1992-11-24

1994-04-05

Shaw, Gareth D.

Boots, shoes, and leggings

395250, 395325, 395425, 395725, 3642396, 3642428, 3642423, 36493701, 3649416, 364DIG2, G06F 1300

Patent

active

053012798

ABSTRACT:
A data processing system including an arrangement for modifying the usual priority arbitration of an input/output channel controller (IOCC) used in granting direct memory access (DMA) service among contending peripheral devices sharing a common peripheral bus. The IOCC includes logic for conditioning the established priority arbitration scheme based upon the data status of the data buffers. If the higher priority requesting device requires a data transfer between the system memory and the IOCC prior to performing an operation directly between the IOCC and the peripheral device, the priority will instead be granted to a lower priority peripheral device that does not require a system memory access operation.

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Multiple Bus DMA Controller, U.S. patent application Ser. No. 303,024 filed Jan. 25, 1989.

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