Excavating
Patent
1994-08-31
1997-07-08
Nguyen, Hoa T.
Excavating
365195, 371 27, G01R 3128, G06F 738, G06F 1100, G11C 700
Patent
active
056469489
ABSTRACT:
A test data pattern, an address pattern, and a control signal are supplied from a pattern generator to a test memory. Data read from the test memory is compared with expected data by an XOR gate. When they match, a compared result that represents pass is output. When they mismatch, a compared result that represents fail is output. A match signal WC detected by the XOR gate is held in a register. The register outputs an inhibition signal to an inhibition gate of the test memory. Thus, a write enable signal WE is inhibited from being supplied to the test memory. In addition, the inhibition signal is supplied to a compared result inhibition gate. The compared result inhibition gate causes the compared result to be passed and prevents the test memory from being excessively written.
REFERENCES:
patent: 4149270 (1979-04-01), Criechi et al.
patent: 4369511 (1983-01-01), Kimura et al.
patent: 4751721 (1988-06-01), Wissell
patent: 4796215 (1989-01-01), Hatta
patent: 4931993 (1990-06-01), Urushima
patent: 5097445 (1992-03-01), Yamauchi
patent: 5111433 (1992-05-01), Miyamoto
patent: 5394361 (1995-02-01), Dickinson
Baba Tadahiko
Kanai Junichi
Kita Kazumi
Kobayashi Shin-ichi
Ohsawa Toshimi
Advantest Corporation
Nguyen Hoa T.
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